411 lines
11 KiB
C
411 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Loongson PCI Host Controller Driver
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*
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* Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
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*/
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#include <linux/of.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/pci-acpi.h>
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#include <linux/pci-ecam.h>
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#include "../pci.h"
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/* Device IDs */
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#define DEV_LS2K_PCIE_PORT0 0x1a05
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#define DEV_LS7A_PCIE_PORT0 0x7a09
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#define DEV_LS7A_PCIE_PORT1 0x7a19
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#define DEV_LS7A_PCIE_PORT2 0x7a29
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#define DEV_LS7A_PCIE_PORT3 0x7a39
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#define DEV_LS7A_PCIE_PORT4 0x7a49
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#define DEV_LS7A_PCIE_PORT5 0x7a59
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#define DEV_LS7A_PCIE_PORT6 0x7a69
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#define DEV_LS2K_APB 0x7a02
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#define DEV_LS7A_GMAC 0x7a03
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#define DEV_LS7A_DC1 0x7a06
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#define DEV_LS7A_LPC 0x7a0c
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#define DEV_LS7A_AHCI 0x7a08
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#define DEV_LS7A_CONF 0x7a10
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#define DEV_LS7A_GNET 0x7a13
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#define DEV_LS7A_EHCI 0x7a14
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#define DEV_LS7A_DC2 0x7a36
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#define DEV_LS7A_HDMI 0x7a37
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#define FLAG_CFG0 BIT(0)
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#define FLAG_CFG1 BIT(1)
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#define FLAG_DEV_FIX BIT(2)
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#define FLAG_DEV_HIDDEN BIT(3)
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struct loongson_pci_data {
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u32 flags;
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struct pci_ops *ops;
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};
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struct loongson_pci {
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void __iomem *cfg0_base;
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void __iomem *cfg1_base;
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struct platform_device *pdev;
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const struct loongson_pci_data *data;
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};
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/* Fixup wrong class code in PCIe bridges */
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static void bridge_class_quirk(struct pci_dev *dev)
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{
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dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_PCIE_PORT0, bridge_class_quirk);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_PCIE_PORT1, bridge_class_quirk);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_PCIE_PORT2, bridge_class_quirk);
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static void system_bus_quirk(struct pci_dev *pdev)
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{
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/*
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* The address space consumed by these devices is outside the
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* resources of the host bridge.
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*/
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pdev->mmio_always_on = 1;
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pdev->non_compliant_bars = 1;
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS2K_APB, system_bus_quirk);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_CONF, system_bus_quirk);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_LPC, system_bus_quirk);
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/*
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* Some Loongson PCIe ports have hardware limitations on their Maximum Read
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* Request Size. They can't handle anything larger than this. Sane
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* firmware will set proper MRRS at boot, so we only need no_inc_mrrs for
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* bridges. However, some MIPS Loongson firmware doesn't set MRRS properly,
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* so we have to enforce maximum safe MRRS, which is 256 bytes.
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*/
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#ifdef CONFIG_MIPS
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static void loongson_set_min_mrrs_quirk(struct pci_dev *pdev)
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{
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struct pci_bus *bus = pdev->bus;
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struct pci_dev *bridge;
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static const struct pci_device_id bridge_devids[] = {
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{ PCI_VDEVICE(LOONGSON, DEV_LS2K_PCIE_PORT0) },
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{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT0) },
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{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT1) },
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{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT2) },
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{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT3) },
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{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT4) },
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{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT5) },
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{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT6) },
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{ 0, },
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};
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/* look for the matching bridge */
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while (!pci_is_root_bus(bus)) {
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bridge = bus->self;
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bus = bus->parent;
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if (pci_match_id(bridge_devids, bridge)) {
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if (pcie_get_readrq(pdev) > 256) {
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pci_info(pdev, "limiting MRRS to 256\n");
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pcie_set_readrq(pdev, 256);
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}
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break;
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}
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}
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}
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DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_set_min_mrrs_quirk);
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#endif
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static void loongson_mrrs_quirk(struct pci_dev *pdev)
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{
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struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
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bridge->no_inc_mrrs = 1;
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS2K_PCIE_PORT0, loongson_mrrs_quirk);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_PCIE_PORT0, loongson_mrrs_quirk);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_PCIE_PORT1, loongson_mrrs_quirk);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_PCIE_PORT2, loongson_mrrs_quirk);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_PCIE_PORT3, loongson_mrrs_quirk);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_PCIE_PORT4, loongson_mrrs_quirk);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_PCIE_PORT5, loongson_mrrs_quirk);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_PCIE_PORT6, loongson_mrrs_quirk);
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static void loongson_pci_pin_quirk(struct pci_dev *pdev)
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{
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pdev->pin = 1 + (PCI_FUNC(pdev->devfn) & 3);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_DC1, loongson_pci_pin_quirk);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_DC2, loongson_pci_pin_quirk);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_GMAC, loongson_pci_pin_quirk);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_AHCI, loongson_pci_pin_quirk);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_EHCI, loongson_pci_pin_quirk);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_GNET, loongson_pci_pin_quirk);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON,
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DEV_LS7A_HDMI, loongson_pci_pin_quirk);
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static void loongson_pci_msi_quirk(struct pci_dev *dev)
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{
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u16 val, class = dev->class >> 8;
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if (class != PCI_CLASS_BRIDGE_HOST)
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return;
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &val);
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val |= PCI_MSI_FLAGS_ENABLE;
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pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, val);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, DEV_LS7A_PCIE_PORT5, loongson_pci_msi_quirk);
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static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus)
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{
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struct pci_config_window *cfg;
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if (acpi_disabled)
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return (struct loongson_pci *)(bus->sysdata);
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cfg = bus->sysdata;
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return (struct loongson_pci *)(cfg->priv);
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}
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static void __iomem *cfg0_map(struct loongson_pci *priv, struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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unsigned long addroff = 0x0;
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unsigned char busnum = bus->number;
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if (!pci_is_root_bus(bus)) {
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addroff |= BIT(24); /* Type 1 Access */
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addroff |= (busnum << 16);
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}
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addroff |= (devfn << 8) | where;
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return priv->cfg0_base + addroff;
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}
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static void __iomem *cfg1_map(struct loongson_pci *priv, struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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unsigned long addroff = 0x0;
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unsigned char busnum = bus->number;
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if (!pci_is_root_bus(bus)) {
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addroff |= BIT(28); /* Type 1 Access */
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addroff |= (busnum << 16);
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}
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addroff |= (devfn << 8) | (where & 0xff) | ((where & 0xf00) << 16);
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return priv->cfg1_base + addroff;
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}
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static bool pdev_may_exist(struct pci_bus *bus, unsigned int device,
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unsigned int function)
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{
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return !(pci_is_root_bus(bus) &&
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(device >= 9 && device <= 20) && (function > 0));
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}
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static void __iomem *pci_loongson_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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unsigned int device = PCI_SLOT(devfn);
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unsigned int function = PCI_FUNC(devfn);
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struct loongson_pci *priv = pci_bus_to_loongson_pci(bus);
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/*
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* Do not read more than one device on the bus other than
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* the host bus.
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*/
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if ((priv->data->flags & FLAG_DEV_FIX) && bus->self) {
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if (!pci_is_root_bus(bus) && (device > 0))
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return NULL;
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}
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/* Don't access non-existent devices */
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if (priv->data->flags & FLAG_DEV_HIDDEN) {
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if (!pdev_may_exist(bus, device, function))
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return NULL;
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}
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/* CFG0 can only access standard space */
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if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
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return cfg0_map(priv, bus, devfn, where);
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/* CFG1 can access extended space */
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if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
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return cfg1_map(priv, bus, devfn, where);
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return NULL;
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}
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#ifdef CONFIG_OF
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static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq;
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u8 val;
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irq = of_irq_parse_and_map_pci(dev, slot, pin);
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if (irq > 0)
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return irq;
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/* Care i8259 legacy systems */
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pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
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/* i8259 only have 15 IRQs */
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if (val > 15)
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return 0;
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return val;
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}
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/* LS2K/LS7A accept 8/16/32-bit PCI config operations */
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static struct pci_ops loongson_pci_ops = {
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.map_bus = pci_loongson_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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};
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/* RS780/SR5690 only accept 32-bit PCI config operations */
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static struct pci_ops loongson_pci_ops32 = {
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.map_bus = pci_loongson_map_bus,
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.read = pci_generic_config_read32,
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.write = pci_generic_config_write32,
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};
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static const struct loongson_pci_data ls2k_pci_data = {
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.flags = FLAG_CFG1 | FLAG_DEV_FIX | FLAG_DEV_HIDDEN,
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.ops = &loongson_pci_ops,
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};
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static const struct loongson_pci_data ls7a_pci_data = {
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.flags = FLAG_CFG1 | FLAG_DEV_FIX | FLAG_DEV_HIDDEN,
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.ops = &loongson_pci_ops,
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};
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static const struct loongson_pci_data rs780e_pci_data = {
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.flags = FLAG_CFG0,
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.ops = &loongson_pci_ops32,
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};
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static const struct of_device_id loongson_pci_of_match[] = {
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{ .compatible = "loongson,ls2k-pci",
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.data = &ls2k_pci_data, },
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{ .compatible = "loongson,ls7a-pci",
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.data = &ls7a_pci_data, },
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{ .compatible = "loongson,rs780e-pci",
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.data = &rs780e_pci_data, },
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{}
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};
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static int loongson_pci_probe(struct platform_device *pdev)
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{
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struct loongson_pci *priv;
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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struct pci_host_bridge *bridge;
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struct resource *regs;
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if (!node)
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return -ENODEV;
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bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
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if (!bridge)
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return -ENODEV;
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priv = pci_host_bridge_priv(bridge);
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priv->pdev = pdev;
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priv->data = of_device_get_match_data(dev);
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if (priv->data->flags & FLAG_CFG0) {
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!regs)
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dev_err(dev, "missing mem resources for cfg0\n");
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else {
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priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
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if (IS_ERR(priv->cfg0_base))
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return PTR_ERR(priv->cfg0_base);
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}
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}
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if (priv->data->flags & FLAG_CFG1) {
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!regs)
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dev_info(dev, "missing mem resource for cfg1\n");
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else {
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priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
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if (IS_ERR(priv->cfg1_base))
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priv->cfg1_base = NULL;
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}
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}
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bridge->sysdata = priv;
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bridge->ops = priv->data->ops;
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bridge->map_irq = loongson_map_irq;
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return pci_host_probe(bridge);
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}
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static struct platform_driver loongson_pci_driver = {
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.driver = {
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.name = "loongson-pci",
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.of_match_table = loongson_pci_of_match,
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},
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.probe = loongson_pci_probe,
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};
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builtin_platform_driver(loongson_pci_driver);
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#endif
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#ifdef CONFIG_ACPI
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static int loongson_pci_ecam_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct loongson_pci *priv;
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struct loongson_pci_data *data;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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cfg->priv = priv;
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data->flags = FLAG_CFG1 | FLAG_DEV_HIDDEN;
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priv->data = data;
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priv->cfg1_base = cfg->win - (cfg->busr.start << 16);
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return 0;
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}
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const struct pci_ecam_ops loongson_pci_ecam_ops = {
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.bus_shift = 16,
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.init = loongson_pci_ecam_init,
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.pci_ops = {
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.map_bus = pci_loongson_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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}
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};
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#endif
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