198 lines
		
	
	
		
			4.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			198 lines
		
	
	
		
			4.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0
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| /*
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|  * PCIe RC driver for Synopsys DesignWare Core
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|  *
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|  * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
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|  *
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|  * Authors: Joao Pinto <Joao.Pinto@synopsys.com>
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|  */
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| #include <linux/clk.h>
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| #include <linux/delay.h>
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| #include <linux/gpio.h>
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| #include <linux/interrupt.h>
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| #include <linux/kernel.h>
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| #include <linux/init.h>
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| #include <linux/of.h>
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| #include <linux/pci.h>
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| #include <linux/platform_device.h>
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| #include <linux/resource.h>
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| #include <linux/types.h>
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| 
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| #include "pcie-designware.h"
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| 
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| struct dw_plat_pcie {
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| 	struct dw_pcie			*pci;
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| 	enum dw_pcie_device_mode	mode;
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| };
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| 
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| struct dw_plat_pcie_of_data {
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| 	enum dw_pcie_device_mode	mode;
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| };
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| 
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| static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
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| };
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| 
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| static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
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| {
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| 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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| 	enum pci_barno bar;
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| 
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| 	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
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| 		dw_pcie_ep_reset_bar(pci, bar);
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| }
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| 
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| static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
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| 				     unsigned int type, u16 interrupt_num)
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| {
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| 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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| 
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| 	switch (type) {
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| 	case PCI_IRQ_INTX:
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| 		return dw_pcie_ep_raise_intx_irq(ep, func_no);
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| 	case PCI_IRQ_MSI:
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| 		return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
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| 	case PCI_IRQ_MSIX:
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| 		return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
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| 	default:
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| 		dev_err(pci->dev, "UNKNOWN IRQ type\n");
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| 	}
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| 
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| 	return 0;
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| }
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| 
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| static const struct pci_epc_features dw_plat_pcie_epc_features = {
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| 	.linkup_notifier = false,
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| 	.msi_capable = true,
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| 	.msix_capable = true,
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| };
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| 
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| static const struct pci_epc_features*
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| dw_plat_pcie_get_features(struct dw_pcie_ep *ep)
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| {
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| 	return &dw_plat_pcie_epc_features;
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| }
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| 
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| static const struct dw_pcie_ep_ops pcie_ep_ops = {
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| 	.init = dw_plat_pcie_ep_init,
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| 	.raise_irq = dw_plat_pcie_ep_raise_irq,
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| 	.get_features = dw_plat_pcie_get_features,
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| };
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| 
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| static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,
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| 				 struct platform_device *pdev)
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| {
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| 	struct dw_pcie *pci = dw_plat_pcie->pci;
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| 	struct dw_pcie_rp *pp = &pci->pp;
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| 	struct device *dev = &pdev->dev;
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| 	int ret;
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| 
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| 	pp->irq = platform_get_irq(pdev, 1);
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| 	if (pp->irq < 0)
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| 		return pp->irq;
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| 
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| 	pp->num_vectors = MAX_MSI_IRQS;
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| 	pp->ops = &dw_plat_pcie_host_ops;
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| 
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| 	ret = dw_pcie_host_init(pp);
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| 	if (ret) {
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| 		dev_err(dev, "Failed to initialize host\n");
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| 		return ret;
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| 	}
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| 
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| 	return 0;
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| }
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| 
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| static int dw_plat_pcie_probe(struct platform_device *pdev)
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| {
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| 	struct device *dev = &pdev->dev;
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| 	struct dw_plat_pcie *dw_plat_pcie;
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| 	struct dw_pcie *pci;
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| 	int ret;
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| 	const struct dw_plat_pcie_of_data *data;
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| 	enum dw_pcie_device_mode mode;
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| 
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| 	data = of_device_get_match_data(dev);
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| 	if (!data)
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| 		return -EINVAL;
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| 
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| 	mode = (enum dw_pcie_device_mode)data->mode;
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| 
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| 	dw_plat_pcie = devm_kzalloc(dev, sizeof(*dw_plat_pcie), GFP_KERNEL);
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| 	if (!dw_plat_pcie)
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| 		return -ENOMEM;
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| 
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| 	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
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| 	if (!pci)
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| 		return -ENOMEM;
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| 
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| 	pci->dev = dev;
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| 
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| 	dw_plat_pcie->pci = pci;
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| 	dw_plat_pcie->mode = mode;
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| 
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| 	platform_set_drvdata(pdev, dw_plat_pcie);
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| 
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| 	switch (dw_plat_pcie->mode) {
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| 	case DW_PCIE_RC_TYPE:
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| 		if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_HOST))
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| 			return -ENODEV;
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| 
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| 		ret = dw_plat_add_pcie_port(dw_plat_pcie, pdev);
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| 		break;
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| 	case DW_PCIE_EP_TYPE:
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| 		if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP))
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| 			return -ENODEV;
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| 
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| 		pci->ep.ops = &pcie_ep_ops;
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| 		ret = dw_pcie_ep_init(&pci->ep);
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| 		if (ret)
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| 			return ret;
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| 
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| 		ret = dw_pcie_ep_init_registers(&pci->ep);
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| 		if (ret) {
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| 			dev_err(dev, "Failed to initialize DWC endpoint registers\n");
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| 			dw_pcie_ep_deinit(&pci->ep);
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| 		}
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| 
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| 		pci_epc_init_notify(pci->ep.epc);
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| 
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| 		break;
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| 	default:
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| 		dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode);
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| 		ret = -EINVAL;
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| 		break;
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| 	}
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| 
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| 	return ret;
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| }
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| 
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| static const struct dw_plat_pcie_of_data dw_plat_pcie_rc_of_data = {
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| 	.mode = DW_PCIE_RC_TYPE,
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| };
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| 
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| static const struct dw_plat_pcie_of_data dw_plat_pcie_ep_of_data = {
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| 	.mode = DW_PCIE_EP_TYPE,
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| };
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| 
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| static const struct of_device_id dw_plat_pcie_of_match[] = {
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| 	{
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| 		.compatible = "snps,dw-pcie",
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| 		.data = &dw_plat_pcie_rc_of_data,
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| 	},
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| 	{
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| 		.compatible = "snps,dw-pcie-ep",
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| 		.data = &dw_plat_pcie_ep_of_data,
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| 	},
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| 	{},
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| };
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| 
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| static struct platform_driver dw_plat_pcie_driver = {
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| 	.driver = {
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| 		.name	= "dw-pcie",
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| 		.of_match_table = dw_plat_pcie_of_match,
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| 		.suppress_bind_attrs = true,
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| 	},
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| 	.probe = dw_plat_pcie_probe,
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| };
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| builtin_platform_driver(dw_plat_pcie_driver);
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