514 lines
14 KiB
C
514 lines
14 KiB
C
/*
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* Qualcomm Atheros IPQ806x GMAC glue layer
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*
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* Copyright (C) 2015 The Linux Foundation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/of_net.h>
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#include <linux/mfd/syscon.h>
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#include <linux/stmmac.h>
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#include <linux/of_mdio.h>
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#include <linux/module.h>
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#include <linux/sys_soc.h>
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#include <linux/bitfield.h>
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#include "stmmac_platform.h"
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#define NSS_COMMON_CLK_GATE 0x8
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#define NSS_COMMON_CLK_GATE_PTP_EN(x) BIT(0x10 + x)
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#define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x) BIT(0x9 + (x * 2))
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#define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x) BIT(0x8 + (x * 2))
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#define NSS_COMMON_CLK_GATE_GMII_RX_EN(x) BIT(0x4 + x)
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#define NSS_COMMON_CLK_GATE_GMII_TX_EN(x) BIT(0x0 + x)
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#define NSS_COMMON_CLK_DIV0 0xC
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#define NSS_COMMON_CLK_DIV_OFFSET(x) (x * 8)
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#define NSS_COMMON_CLK_DIV_MASK 0x7f
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#define NSS_COMMON_CLK_SRC_CTRL 0x14
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#define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x) (x)
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/* Mode is coded on 1 bit but is different depending on the MAC ID:
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* MAC0: QSGMII=0 RGMII=1
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* MAC1: QSGMII=0 SGMII=0 RGMII=1
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* MAC2 & MAC3: QSGMII=0 SGMII=1
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*/
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#define NSS_COMMON_CLK_SRC_CTRL_RGMII(x) 1
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#define NSS_COMMON_CLK_SRC_CTRL_SGMII(x) ((x >= 2) ? 1 : 0)
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#define NSS_COMMON_GMAC_CTL(x) (0x30 + (x * 4))
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#define NSS_COMMON_GMAC_CTL_CSYS_REQ BIT(19)
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#define NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL BIT(16)
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#define NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET 8
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#define NSS_COMMON_GMAC_CTL_IFG_OFFSET 0
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#define NSS_COMMON_CLK_DIV_RGMII_1000 1
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#define NSS_COMMON_CLK_DIV_RGMII_100 9
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#define NSS_COMMON_CLK_DIV_RGMII_10 99
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#define NSS_COMMON_CLK_DIV_SGMII_1000 0
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#define NSS_COMMON_CLK_DIV_SGMII_100 4
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#define NSS_COMMON_CLK_DIV_SGMII_10 49
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#define QSGMII_PCS_ALL_CH_CTL 0x80
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#define QSGMII_PCS_CH_SPEED_FORCE BIT(1)
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#define QSGMII_PCS_CH_SPEED_10 0x0
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#define QSGMII_PCS_CH_SPEED_100 BIT(2)
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#define QSGMII_PCS_CH_SPEED_1000 BIT(3)
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#define QSGMII_PCS_CH_SPEED_MASK (QSGMII_PCS_CH_SPEED_FORCE | \
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QSGMII_PCS_CH_SPEED_10 | \
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QSGMII_PCS_CH_SPEED_100 | \
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QSGMII_PCS_CH_SPEED_1000)
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#define QSGMII_PCS_CH_SPEED_SHIFT(x) ((x) * 4)
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#define QSGMII_PCS_CAL_LCKDT_CTL 0x120
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#define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19)
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/* Only GMAC1/2/3 support SGMII and their CTL register are not contiguous */
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#define QSGMII_PHY_SGMII_CTL(x) ((x == 1) ? 0x134 : \
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(0x13c + (4 * (x - 2))))
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#define QSGMII_PHY_CDR_EN BIT(0)
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#define QSGMII_PHY_RX_FRONT_EN BIT(1)
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#define QSGMII_PHY_RX_SIGNAL_DETECT_EN BIT(2)
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#define QSGMII_PHY_TX_DRIVER_EN BIT(3)
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#define QSGMII_PHY_QSGMII_EN BIT(7)
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#define QSGMII_PHY_DEEMPHASIS_LVL_MASK GENMASK(11, 10)
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#define QSGMII_PHY_DEEMPHASIS_LVL(x) FIELD_PREP(QSGMII_PHY_DEEMPHASIS_LVL_MASK, (x))
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#define QSGMII_PHY_PHASE_LOOP_GAIN_MASK GENMASK(14, 12)
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#define QSGMII_PHY_PHASE_LOOP_GAIN(x) FIELD_PREP(QSGMII_PHY_PHASE_LOOP_GAIN_MASK, (x))
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#define QSGMII_PHY_RX_DC_BIAS_MASK GENMASK(19, 18)
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#define QSGMII_PHY_RX_DC_BIAS(x) FIELD_PREP(QSGMII_PHY_RX_DC_BIAS_MASK, (x))
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#define QSGMII_PHY_RX_INPUT_EQU_MASK GENMASK(21, 20)
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#define QSGMII_PHY_RX_INPUT_EQU(x) FIELD_PREP(QSGMII_PHY_RX_INPUT_EQU_MASK, (x))
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#define QSGMII_PHY_CDR_PI_SLEW_MASK GENMASK(23, 22)
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#define QSGMII_PHY_CDR_PI_SLEW(x) FIELD_PREP(QSGMII_PHY_CDR_PI_SLEW_MASK, (x))
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#define QSGMII_PHY_TX_SLEW_MASK GENMASK(27, 26)
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#define QSGMII_PHY_TX_SLEW(x) FIELD_PREP(QSGMII_PHY_TX_SLEW_MASK, (x))
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#define QSGMII_PHY_TX_DRV_AMP_MASK GENMASK(31, 28)
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#define QSGMII_PHY_TX_DRV_AMP(x) FIELD_PREP(QSGMII_PHY_TX_DRV_AMP_MASK, (x))
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struct ipq806x_gmac {
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struct platform_device *pdev;
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struct regmap *nss_common;
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struct regmap *qsgmii_csr;
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uint32_t id;
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struct clk *core_clk;
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phy_interface_t phy_mode;
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};
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static int get_clk_div_sgmii(struct ipq806x_gmac *gmac, unsigned int speed)
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{
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struct device *dev = &gmac->pdev->dev;
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int div;
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switch (speed) {
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case SPEED_1000:
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div = NSS_COMMON_CLK_DIV_SGMII_1000;
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break;
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case SPEED_100:
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div = NSS_COMMON_CLK_DIV_SGMII_100;
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break;
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case SPEED_10:
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div = NSS_COMMON_CLK_DIV_SGMII_10;
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break;
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default:
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dev_err(dev, "Speed %dMbps not supported in SGMII\n", speed);
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return -EINVAL;
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}
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return div;
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}
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static int get_clk_div_rgmii(struct ipq806x_gmac *gmac, unsigned int speed)
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{
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struct device *dev = &gmac->pdev->dev;
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int div;
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switch (speed) {
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case SPEED_1000:
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div = NSS_COMMON_CLK_DIV_RGMII_1000;
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break;
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case SPEED_100:
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div = NSS_COMMON_CLK_DIV_RGMII_100;
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break;
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case SPEED_10:
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div = NSS_COMMON_CLK_DIV_RGMII_10;
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break;
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default:
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dev_err(dev, "Speed %dMbps not supported in RGMII\n", speed);
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return -EINVAL;
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}
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return div;
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}
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static int ipq806x_gmac_set_speed(struct ipq806x_gmac *gmac, unsigned int speed)
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{
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uint32_t clk_bits, val;
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int div;
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switch (gmac->phy_mode) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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div = get_clk_div_rgmii(gmac, speed);
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clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |
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NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);
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break;
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case PHY_INTERFACE_MODE_SGMII:
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div = get_clk_div_sgmii(gmac, speed);
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clk_bits = NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) |
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NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id);
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break;
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default:
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dev_err(&gmac->pdev->dev, "Unsupported PHY mode: \"%s\"\n",
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phy_modes(gmac->phy_mode));
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return -EINVAL;
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}
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/* Disable the clocks */
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regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
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val &= ~clk_bits;
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regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
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/* Set the divider */
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regmap_read(gmac->nss_common, NSS_COMMON_CLK_DIV0, &val);
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val &= ~(NSS_COMMON_CLK_DIV_MASK
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<< NSS_COMMON_CLK_DIV_OFFSET(gmac->id));
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val |= div << NSS_COMMON_CLK_DIV_OFFSET(gmac->id);
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regmap_write(gmac->nss_common, NSS_COMMON_CLK_DIV0, val);
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/* Enable the clock back */
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regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
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val |= clk_bits;
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regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
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return 0;
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}
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static int ipq806x_gmac_of_parse(struct ipq806x_gmac *gmac)
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{
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struct device *dev = &gmac->pdev->dev;
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int ret;
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ret = of_get_phy_mode(dev->of_node, &gmac->phy_mode);
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if (ret) {
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dev_err(dev, "missing phy mode property\n");
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return -EINVAL;
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}
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if (of_property_read_u32(dev->of_node, "qcom,id", &gmac->id) < 0) {
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dev_err(dev, "missing qcom id property\n");
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return -EINVAL;
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}
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/* The GMACs are called 1 to 4 in the documentation, but to simplify the
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* code and keep it consistent with the Linux convention, we'll number
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* them from 0 to 3 here.
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*/
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if (gmac->id > 3) {
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dev_err(dev, "invalid gmac id\n");
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return -EINVAL;
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}
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gmac->core_clk = devm_clk_get(dev, "stmmaceth");
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if (IS_ERR(gmac->core_clk)) {
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dev_err(dev, "missing stmmaceth clk property\n");
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return PTR_ERR(gmac->core_clk);
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}
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clk_set_rate(gmac->core_clk, 266000000);
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/* Setup the register map for the nss common registers */
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gmac->nss_common = syscon_regmap_lookup_by_phandle(dev->of_node,
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"qcom,nss-common");
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if (IS_ERR(gmac->nss_common)) {
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dev_err(dev, "missing nss-common node\n");
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return PTR_ERR(gmac->nss_common);
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}
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/* Setup the register map for the qsgmii csr registers */
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gmac->qsgmii_csr = syscon_regmap_lookup_by_phandle(dev->of_node,
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"qcom,qsgmii-csr");
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if (IS_ERR(gmac->qsgmii_csr))
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dev_err(dev, "missing qsgmii-csr node\n");
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return PTR_ERR_OR_ZERO(gmac->qsgmii_csr);
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}
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static void ipq806x_gmac_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode)
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{
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struct ipq806x_gmac *gmac = priv;
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ipq806x_gmac_set_speed(gmac, speed);
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}
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static int
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ipq806x_gmac_configure_qsgmii_pcs_speed(struct ipq806x_gmac *gmac)
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{
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struct platform_device *pdev = gmac->pdev;
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struct device *dev = &pdev->dev;
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struct device_node *dn;
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int link_speed;
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int val = 0;
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int ret;
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/* Some bootloader may apply wrong configuration and cause
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* not functioning port. If fixed link is not set,
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* reset the force speed bit.
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*/
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if (!of_phy_is_fixed_link(pdev->dev.of_node))
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goto write;
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dn = of_get_child_by_name(pdev->dev.of_node, "fixed-link");
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ret = of_property_read_u32(dn, "speed", &link_speed);
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of_node_put(dn);
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if (ret) {
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dev_err(dev, "found fixed-link node with no speed");
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return ret;
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}
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val = QSGMII_PCS_CH_SPEED_FORCE;
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switch (link_speed) {
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case SPEED_1000:
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val |= QSGMII_PCS_CH_SPEED_1000;
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break;
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case SPEED_100:
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val |= QSGMII_PCS_CH_SPEED_100;
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break;
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case SPEED_10:
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val |= QSGMII_PCS_CH_SPEED_10;
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break;
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}
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write:
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regmap_update_bits(gmac->qsgmii_csr, QSGMII_PCS_ALL_CH_CTL,
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QSGMII_PCS_CH_SPEED_MASK <<
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QSGMII_PCS_CH_SPEED_SHIFT(gmac->id),
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val <<
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QSGMII_PCS_CH_SPEED_SHIFT(gmac->id));
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return 0;
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}
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static const struct soc_device_attribute ipq806x_gmac_soc_v1[] = {
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{
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.revision = "1.*",
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},
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{
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/* sentinel */
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}
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};
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static int
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ipq806x_gmac_configure_qsgmii_params(struct ipq806x_gmac *gmac)
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{
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struct platform_device *pdev = gmac->pdev;
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const struct soc_device_attribute *soc;
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struct device *dev = &pdev->dev;
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u32 qsgmii_param;
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switch (gmac->id) {
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case 1:
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soc = soc_device_match(ipq806x_gmac_soc_v1);
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if (soc)
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qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xc) |
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QSGMII_PHY_TX_SLEW(0x2) |
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QSGMII_PHY_DEEMPHASIS_LVL(0x2);
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else
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qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xd) |
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QSGMII_PHY_TX_SLEW(0x0) |
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QSGMII_PHY_DEEMPHASIS_LVL(0x0);
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qsgmii_param |= QSGMII_PHY_RX_DC_BIAS(0x2);
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break;
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case 2:
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case 3:
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qsgmii_param = QSGMII_PHY_RX_DC_BIAS(0x3) |
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QSGMII_PHY_TX_DRV_AMP(0xc);
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break;
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default: /* gmac 0 can't be set in SGMII mode */
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dev_err(dev, "gmac id %d can't be in SGMII mode", gmac->id);
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return -EINVAL;
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}
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/* Common params across all gmac id */
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qsgmii_param |= QSGMII_PHY_CDR_EN |
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QSGMII_PHY_RX_FRONT_EN |
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QSGMII_PHY_RX_SIGNAL_DETECT_EN |
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QSGMII_PHY_TX_DRIVER_EN |
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QSGMII_PHY_QSGMII_EN |
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QSGMII_PHY_PHASE_LOOP_GAIN(0x4) |
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QSGMII_PHY_RX_INPUT_EQU(0x1) |
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QSGMII_PHY_CDR_PI_SLEW(0x2);
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regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id),
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qsgmii_param);
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return 0;
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}
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static int ipq806x_gmac_probe(struct platform_device *pdev)
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{
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struct plat_stmmacenet_data *plat_dat;
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struct stmmac_resources stmmac_res;
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struct device *dev = &pdev->dev;
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struct ipq806x_gmac *gmac;
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int val;
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int err;
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val = stmmac_get_platform_resources(pdev, &stmmac_res);
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if (val)
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return val;
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plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
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if (IS_ERR(plat_dat))
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return PTR_ERR(plat_dat);
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gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
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if (!gmac)
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return -ENOMEM;
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gmac->pdev = pdev;
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err = ipq806x_gmac_of_parse(gmac);
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if (err) {
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dev_err(dev, "device tree parsing error\n");
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return err;
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}
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regmap_write(gmac->qsgmii_csr, QSGMII_PCS_CAL_LCKDT_CTL,
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QSGMII_PCS_CAL_LCKDT_CTL_RST);
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/* Inter frame gap is set to 12 */
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val = 12 << NSS_COMMON_GMAC_CTL_IFG_OFFSET |
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12 << NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET;
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/* We also initiate an AXI low power exit request */
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val |= NSS_COMMON_GMAC_CTL_CSYS_REQ;
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switch (gmac->phy_mode) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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val |= NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
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break;
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case PHY_INTERFACE_MODE_SGMII:
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val &= ~NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
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break;
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default:
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goto err_unsupported_phy;
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}
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regmap_write(gmac->nss_common, NSS_COMMON_GMAC_CTL(gmac->id), val);
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/* Configure the clock src according to the mode */
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regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val);
|
|
val &= ~(1 << NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id));
|
|
switch (gmac->phy_mode) {
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
|
val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) <<
|
|
NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
|
|
break;
|
|
case PHY_INTERFACE_MODE_SGMII:
|
|
val |= NSS_COMMON_CLK_SRC_CTRL_SGMII(gmac->id) <<
|
|
NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
|
|
break;
|
|
default:
|
|
goto err_unsupported_phy;
|
|
}
|
|
regmap_write(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, val);
|
|
|
|
/* Enable PTP clock */
|
|
regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
|
|
val |= NSS_COMMON_CLK_GATE_PTP_EN(gmac->id);
|
|
switch (gmac->phy_mode) {
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
|
val |= NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |
|
|
NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);
|
|
break;
|
|
case PHY_INTERFACE_MODE_SGMII:
|
|
val |= NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) |
|
|
NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id);
|
|
break;
|
|
default:
|
|
goto err_unsupported_phy;
|
|
}
|
|
regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
|
|
|
|
if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) {
|
|
err = ipq806x_gmac_configure_qsgmii_params(gmac);
|
|
if (err)
|
|
return err;
|
|
|
|
err = ipq806x_gmac_configure_qsgmii_pcs_speed(gmac);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
plat_dat->has_gmac = true;
|
|
plat_dat->bsp_priv = gmac;
|
|
plat_dat->fix_mac_speed = ipq806x_gmac_fix_mac_speed;
|
|
plat_dat->multicast_filter_bins = 0;
|
|
plat_dat->tx_fifo_size = 8192;
|
|
plat_dat->rx_fifo_size = 8192;
|
|
|
|
return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
|
|
|
|
err_unsupported_phy:
|
|
dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n",
|
|
phy_modes(gmac->phy_mode));
|
|
return -EINVAL;
|
|
}
|
|
|
|
static const struct of_device_id ipq806x_gmac_dwmac_match[] = {
|
|
{ .compatible = "qcom,ipq806x-gmac" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ipq806x_gmac_dwmac_match);
|
|
|
|
static struct platform_driver ipq806x_gmac_dwmac_driver = {
|
|
.probe = ipq806x_gmac_probe,
|
|
.remove_new = stmmac_pltfr_remove,
|
|
.driver = {
|
|
.name = "ipq806x-gmac-dwmac",
|
|
.pm = &stmmac_pltfr_pm_ops,
|
|
.of_match_table = ipq806x_gmac_dwmac_match,
|
|
},
|
|
};
|
|
module_platform_driver(ipq806x_gmac_dwmac_driver);
|
|
|
|
MODULE_AUTHOR("Mathieu Olivari <mathieu@codeaurora.org>");
|
|
MODULE_DESCRIPTION("Qualcomm Atheros IPQ806x DWMAC specific glue layer");
|
|
MODULE_LICENSE("Dual BSD/GPL");
|