645 lines
18 KiB
C
645 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*******************************************************************************
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STMMAC Common Header File
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#ifndef __COMMON_H__
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#define __COMMON_H__
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#include <linux/etherdevice.h>
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#include <linux/netdevice.h>
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#include <linux/stmmac.h>
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#include <linux/phy.h>
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#include <linux/pcs/pcs-xpcs.h>
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#include <linux/module.h>
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#if IS_ENABLED(CONFIG_VLAN_8021Q)
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#define STMMAC_VLAN_TAG_USED
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#include <linux/if_vlan.h>
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#endif
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#include "descs.h"
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#include "hwif.h"
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#include "mmc.h"
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/* Synopsys Core versions */
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#define DWMAC_CORE_3_40 0x34
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#define DWMAC_CORE_3_50 0x35
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#define DWMAC_CORE_3_70 0x37
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#define DWMAC_CORE_4_00 0x40
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#define DWMAC_CORE_4_10 0x41
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#define DWMAC_CORE_5_00 0x50
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#define DWMAC_CORE_5_10 0x51
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#define DWMAC_CORE_5_20 0x52
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#define DWXGMAC_CORE_2_10 0x21
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#define DWXGMAC_CORE_2_20 0x22
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#define DWXLGMAC_CORE_2_00 0x20
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/* Device ID */
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#define DWXGMAC_ID 0x76
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#define DWXLGMAC_ID 0x27
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#define STMMAC_CHAN0 0 /* Always supported and default for all chips */
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/* TX and RX Descriptor Length, these need to be power of two.
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* TX descriptor length less than 64 may cause transmit queue timed out error.
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* RX descriptor length less than 64 may cause inconsistent Rx chain error.
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*/
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#define DMA_MIN_TX_SIZE 64
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#define DMA_MAX_TX_SIZE 1024
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#define DMA_DEFAULT_TX_SIZE 512
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#define DMA_MIN_RX_SIZE 64
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#define DMA_MAX_RX_SIZE 1024
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#define DMA_DEFAULT_RX_SIZE 512
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#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
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#undef FRAME_FILTER_DEBUG
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/* #define FRAME_FILTER_DEBUG */
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struct stmmac_q_tx_stats {
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u64_stats_t tx_bytes;
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u64_stats_t tx_set_ic_bit;
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u64_stats_t tx_tso_frames;
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u64_stats_t tx_tso_nfrags;
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};
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struct stmmac_napi_tx_stats {
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u64_stats_t tx_packets;
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u64_stats_t tx_pkt_n;
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u64_stats_t poll;
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u64_stats_t tx_clean;
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u64_stats_t tx_set_ic_bit;
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};
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struct stmmac_txq_stats {
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/* Updates protected by tx queue lock. */
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struct u64_stats_sync q_syncp;
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struct stmmac_q_tx_stats q;
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/* Updates protected by NAPI poll logic. */
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struct u64_stats_sync napi_syncp;
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struct stmmac_napi_tx_stats napi;
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} ____cacheline_aligned_in_smp;
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struct stmmac_napi_rx_stats {
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u64_stats_t rx_bytes;
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u64_stats_t rx_packets;
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u64_stats_t rx_pkt_n;
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u64_stats_t poll;
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};
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struct stmmac_rxq_stats {
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/* Updates protected by NAPI poll logic. */
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struct u64_stats_sync napi_syncp;
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struct stmmac_napi_rx_stats napi;
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} ____cacheline_aligned_in_smp;
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/* Updates on each CPU protected by not allowing nested irqs. */
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struct stmmac_pcpu_stats {
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struct u64_stats_sync syncp;
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u64_stats_t rx_normal_irq_n[MTL_MAX_TX_QUEUES];
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u64_stats_t tx_normal_irq_n[MTL_MAX_RX_QUEUES];
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};
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/* Extra statistic and debug information exposed by ethtool */
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struct stmmac_extra_stats {
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/* Transmit errors */
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unsigned long tx_underflow ____cacheline_aligned;
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unsigned long tx_carrier;
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unsigned long tx_losscarrier;
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unsigned long vlan_tag;
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unsigned long tx_deferred;
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unsigned long tx_vlan;
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unsigned long tx_jabber;
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unsigned long tx_frame_flushed;
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unsigned long tx_payload_error;
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unsigned long tx_ip_header_error;
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unsigned long tx_collision;
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/* Receive errors */
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unsigned long rx_desc;
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unsigned long sa_filter_fail;
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unsigned long overflow_error;
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unsigned long ipc_csum_error;
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unsigned long rx_collision;
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unsigned long rx_crc_errors;
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unsigned long dribbling_bit;
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unsigned long rx_length;
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unsigned long rx_mii;
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unsigned long rx_multicast;
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unsigned long rx_gmac_overflow;
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unsigned long rx_watchdog;
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unsigned long da_rx_filter_fail;
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unsigned long sa_rx_filter_fail;
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unsigned long rx_missed_cntr;
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unsigned long rx_overflow_cntr;
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unsigned long rx_vlan;
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unsigned long rx_split_hdr_pkt_n;
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/* Tx/Rx IRQ error info */
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unsigned long tx_undeflow_irq;
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unsigned long tx_process_stopped_irq;
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unsigned long tx_jabber_irq;
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unsigned long rx_overflow_irq;
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unsigned long rx_buf_unav_irq;
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unsigned long rx_process_stopped_irq;
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unsigned long rx_watchdog_irq;
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unsigned long tx_early_irq;
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unsigned long fatal_bus_error_irq;
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/* Tx/Rx IRQ Events */
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unsigned long rx_early_irq;
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unsigned long threshold;
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unsigned long irq_receive_pmt_irq_n;
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/* MMC info */
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unsigned long mmc_tx_irq_n;
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unsigned long mmc_rx_irq_n;
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unsigned long mmc_rx_csum_offload_irq_n;
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/* EEE */
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unsigned long irq_tx_path_in_lpi_mode_n;
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unsigned long irq_tx_path_exit_lpi_mode_n;
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unsigned long irq_rx_path_in_lpi_mode_n;
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unsigned long irq_rx_path_exit_lpi_mode_n;
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unsigned long phy_eee_wakeup_error_n;
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/* Extended RDES status */
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unsigned long ip_hdr_err;
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unsigned long ip_payload_err;
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unsigned long ip_csum_bypassed;
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unsigned long ipv4_pkt_rcvd;
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unsigned long ipv6_pkt_rcvd;
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unsigned long no_ptp_rx_msg_type_ext;
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unsigned long ptp_rx_msg_type_sync;
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unsigned long ptp_rx_msg_type_follow_up;
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unsigned long ptp_rx_msg_type_delay_req;
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unsigned long ptp_rx_msg_type_delay_resp;
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unsigned long ptp_rx_msg_type_pdelay_req;
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unsigned long ptp_rx_msg_type_pdelay_resp;
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unsigned long ptp_rx_msg_type_pdelay_follow_up;
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unsigned long ptp_rx_msg_type_announce;
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unsigned long ptp_rx_msg_type_management;
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unsigned long ptp_rx_msg_pkt_reserved_type;
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unsigned long ptp_frame_type;
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unsigned long ptp_ver;
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unsigned long timestamp_dropped;
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unsigned long av_pkt_rcvd;
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unsigned long av_tagged_pkt_rcvd;
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unsigned long vlan_tag_priority_val;
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unsigned long l3_filter_match;
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unsigned long l4_filter_match;
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unsigned long l3_l4_filter_no_match;
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/* PCS */
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unsigned long irq_pcs_ane_n;
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unsigned long irq_pcs_link_n;
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unsigned long irq_rgmii_n;
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unsigned long pcs_link;
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unsigned long pcs_duplex;
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unsigned long pcs_speed;
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/* debug register */
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unsigned long mtl_tx_status_fifo_full;
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unsigned long mtl_tx_fifo_not_empty;
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unsigned long mmtl_fifo_ctrl;
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unsigned long mtl_tx_fifo_read_ctrl_write;
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unsigned long mtl_tx_fifo_read_ctrl_wait;
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unsigned long mtl_tx_fifo_read_ctrl_read;
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unsigned long mtl_tx_fifo_read_ctrl_idle;
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unsigned long mac_tx_in_pause;
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unsigned long mac_tx_frame_ctrl_xfer;
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unsigned long mac_tx_frame_ctrl_idle;
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unsigned long mac_tx_frame_ctrl_wait;
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unsigned long mac_tx_frame_ctrl_pause;
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unsigned long mac_gmii_tx_proto_engine;
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unsigned long mtl_rx_fifo_fill_level_full;
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unsigned long mtl_rx_fifo_fill_above_thresh;
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unsigned long mtl_rx_fifo_fill_below_thresh;
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unsigned long mtl_rx_fifo_fill_level_empty;
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unsigned long mtl_rx_fifo_read_ctrl_flush;
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unsigned long mtl_rx_fifo_read_ctrl_read_data;
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unsigned long mtl_rx_fifo_read_ctrl_status;
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unsigned long mtl_rx_fifo_read_ctrl_idle;
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unsigned long mtl_rx_fifo_ctrl_active;
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unsigned long mac_rx_frame_ctrl_fifo;
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unsigned long mac_gmii_rx_proto_engine;
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/* EST */
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unsigned long mtl_est_cgce;
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unsigned long mtl_est_hlbs;
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unsigned long mtl_est_hlbf;
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unsigned long mtl_est_btre;
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unsigned long mtl_est_btrlm;
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unsigned long max_sdu_txq_drop[MTL_MAX_TX_QUEUES];
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unsigned long mtl_est_txq_hlbf[MTL_MAX_TX_QUEUES];
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/* per queue statistics */
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struct stmmac_txq_stats txq_stats[MTL_MAX_TX_QUEUES];
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struct stmmac_rxq_stats rxq_stats[MTL_MAX_RX_QUEUES];
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struct stmmac_pcpu_stats __percpu *pcpu_stats;
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unsigned long rx_dropped;
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unsigned long rx_errors;
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unsigned long tx_dropped;
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unsigned long tx_errors;
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};
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/* Safety Feature statistics exposed by ethtool */
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struct stmmac_safety_stats {
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unsigned long mac_errors[32];
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unsigned long mtl_errors[32];
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unsigned long dma_errors[32];
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unsigned long dma_dpp_errors[32];
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};
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/* Number of fields in Safety Stats */
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#define STMMAC_SAFETY_FEAT_SIZE \
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(sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
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/* CSR Frequency Access Defines*/
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#define CSR_F_35M 35000000
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#define CSR_F_60M 60000000
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#define CSR_F_100M 100000000
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#define CSR_F_150M 150000000
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#define CSR_F_250M 250000000
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#define CSR_F_300M 300000000
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#define MAC_CSR_H_FRQ_MASK 0x20
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#define HASH_TABLE_SIZE 64
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#define PAUSE_TIME 0xffff
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/* Flow Control defines */
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#define FLOW_OFF 0
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#define FLOW_RX 1
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#define FLOW_TX 2
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#define FLOW_AUTO (FLOW_TX | FLOW_RX)
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/* PCS defines */
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#define STMMAC_PCS_RGMII (1 << 0)
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#define STMMAC_PCS_SGMII (1 << 1)
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#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
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/* DMA HW feature register fields */
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#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
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#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
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#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
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#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
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#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
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#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
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#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
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#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
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#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
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#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
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#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
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#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
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#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
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#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
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#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
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#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
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#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
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#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
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#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
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#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
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#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
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#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
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#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
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/* Timestamping with Internal System Time */
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#define DMA_HW_FEAT_INTTSEN 0x02000000
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#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
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#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
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#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
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#define DEFAULT_DMA_PBL 8
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/* MSI defines */
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#define STMMAC_MSI_VEC_MAX 32
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/* PCS status and mask defines */
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#define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
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#define PCS_LINK_IRQ BIT(1) /* PCS Link */
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#define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
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/* Max/Min RI Watchdog Timer count value */
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#define MAX_DMA_RIWT 0xff
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#define MIN_DMA_RIWT 0x10
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#define DEF_DMA_RIWT 0xa0
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/* Tx coalesce parameters */
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#define STMMAC_COAL_TX_TIMER 5000
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#define STMMAC_MAX_COAL_TX_TICK 100000
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#define STMMAC_TX_MAX_FRAMES 256
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#define STMMAC_TX_FRAMES 25
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#define STMMAC_RX_FRAMES 0
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/* Packets types */
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enum packets_types {
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PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
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PACKET_PTPQ = 0x2, /* PTP Packets */
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PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
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PACKET_UPQ = 0x4, /* Untagged Packets */
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PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
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};
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/* Rx IPC status */
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enum rx_frame_status {
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good_frame = 0x0,
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discard_frame = 0x1,
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csum_none = 0x2,
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llc_snap = 0x4,
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dma_own = 0x8,
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rx_not_ls = 0x10,
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};
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/* Tx status */
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enum tx_frame_status {
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tx_done = 0x0,
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tx_not_ls = 0x1,
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tx_err = 0x2,
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tx_dma_own = 0x4,
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tx_err_bump_tc = 0x8,
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};
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enum dma_irq_status {
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tx_hard_error = 0x1,
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tx_hard_error_bump_tc = 0x2,
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handle_rx = 0x4,
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handle_tx = 0x8,
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};
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enum dma_irq_dir {
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DMA_DIR_RX = 0x1,
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DMA_DIR_TX = 0x2,
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DMA_DIR_RXTX = 0x3,
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};
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enum request_irq_err {
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REQ_IRQ_ERR_ALL,
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REQ_IRQ_ERR_TX,
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REQ_IRQ_ERR_RX,
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REQ_IRQ_ERR_SFTY,
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REQ_IRQ_ERR_SFTY_UE,
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REQ_IRQ_ERR_SFTY_CE,
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REQ_IRQ_ERR_LPI,
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REQ_IRQ_ERR_WOL,
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REQ_IRQ_ERR_MAC,
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REQ_IRQ_ERR_NO,
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};
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/* EEE and LPI defines */
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#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
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#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
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#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
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#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
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/* FPE defines */
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#define FPE_EVENT_UNKNOWN 0
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#define FPE_EVENT_TRSP BIT(0)
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#define FPE_EVENT_TVER BIT(1)
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#define FPE_EVENT_RRSP BIT(2)
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#define FPE_EVENT_RVER BIT(3)
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#define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
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/* Physical Coding Sublayer */
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struct rgmii_adv {
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unsigned int pause;
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unsigned int duplex;
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unsigned int lp_pause;
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unsigned int lp_duplex;
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};
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#define STMMAC_PCS_PAUSE 1
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#define STMMAC_PCS_ASYM_PAUSE 2
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/* DMA HW capabilities */
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struct dma_features {
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unsigned int mbps_10_100;
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unsigned int mbps_1000;
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unsigned int half_duplex;
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unsigned int hash_filter;
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unsigned int multi_addr;
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unsigned int pcs;
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unsigned int sma_mdio;
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unsigned int pmt_remote_wake_up;
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unsigned int pmt_magic_frame;
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unsigned int rmon;
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/* IEEE 1588-2002 */
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unsigned int time_stamp;
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/* IEEE 1588-2008 */
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unsigned int atime_stamp;
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/* 802.3az - Energy-Efficient Ethernet (EEE) */
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unsigned int eee;
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unsigned int av;
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unsigned int hash_tb_sz;
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unsigned int tsoen;
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/* TX and RX csum */
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unsigned int tx_coe;
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unsigned int rx_coe;
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unsigned int rx_coe_type1;
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unsigned int rx_coe_type2;
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unsigned int rxfifo_over_2048;
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/* TX and RX number of channels */
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unsigned int number_rx_channel;
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unsigned int number_tx_channel;
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/* TX and RX number of queues */
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unsigned int number_rx_queues;
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unsigned int number_tx_queues;
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/* PPS output */
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unsigned int pps_out_num;
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/* Number of Traffic Classes */
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unsigned int numtc;
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/* DCB Feature Enable */
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unsigned int dcben;
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/* IEEE 1588 High Word Register Enable */
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unsigned int advthword;
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/* PTP Offload Enable */
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unsigned int ptoen;
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/* One-Step Timestamping Enable */
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unsigned int osten;
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/* Priority-Based Flow Control Enable */
|
|
unsigned int pfcen;
|
|
/* Alternate (enhanced) DESC mode */
|
|
unsigned int enh_desc;
|
|
/* TX and RX FIFO sizes */
|
|
unsigned int tx_fifo_size;
|
|
unsigned int rx_fifo_size;
|
|
/* Automotive Safety Package */
|
|
unsigned int asp;
|
|
/* RX Parser */
|
|
unsigned int frpsel;
|
|
unsigned int frpbs;
|
|
unsigned int frpes;
|
|
unsigned int addr64;
|
|
unsigned int host_dma_width;
|
|
unsigned int rssen;
|
|
unsigned int vlhash;
|
|
unsigned int sphen;
|
|
unsigned int vlins;
|
|
unsigned int dvlan;
|
|
unsigned int l3l4fnum;
|
|
unsigned int arpoffsel;
|
|
/* One Step for PTP over UDP/IP Feature Enable */
|
|
unsigned int pou_ost_en;
|
|
/* Tx Timestamp FIFO Depth */
|
|
unsigned int ttsfd;
|
|
/* Queue/Channel-Based VLAN tag insertion on Tx */
|
|
unsigned int cbtisel;
|
|
/* Supported Parallel Instruction Processor Engines */
|
|
unsigned int frppipe_num;
|
|
/* Number of Extended VLAN Tag Filters */
|
|
unsigned int nrvf_num;
|
|
/* TSN Features */
|
|
unsigned int estwid;
|
|
unsigned int estdep;
|
|
unsigned int estsel;
|
|
unsigned int fpesel;
|
|
unsigned int tbssel;
|
|
/* Number of DMA channels enabled for TBS */
|
|
unsigned int tbs_ch_num;
|
|
/* Per-Stream Filtering Enable */
|
|
unsigned int sgfsel;
|
|
/* Numbers of Auxiliary Snapshot Inputs */
|
|
unsigned int aux_snapshot_n;
|
|
/* Timestamp System Time Source */
|
|
unsigned int tssrc;
|
|
/* Enhanced DMA Enable */
|
|
unsigned int edma;
|
|
/* Different Descriptor Cache Enable */
|
|
unsigned int ediffc;
|
|
/* VxLAN/NVGRE Enable */
|
|
unsigned int vxn;
|
|
/* Debug Memory Interface Enable */
|
|
unsigned int dbgmem;
|
|
/* Number of Policing Counters */
|
|
unsigned int pcsel;
|
|
};
|
|
|
|
/* RX Buffer size must be multiple of 4/8/16 bytes */
|
|
#define BUF_SIZE_16KiB 16368
|
|
#define BUF_SIZE_8KiB 8188
|
|
#define BUF_SIZE_4KiB 4096
|
|
#define BUF_SIZE_2KiB 2048
|
|
|
|
/* Power Down and WOL */
|
|
#define PMT_NOT_SUPPORTED 0
|
|
#define PMT_SUPPORTED 1
|
|
|
|
/* Common MAC defines */
|
|
#define MAC_CTRL_REG 0x00000000 /* MAC Control */
|
|
#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
|
|
#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
|
|
|
|
/* Default LPI timers */
|
|
#define STMMAC_DEFAULT_LIT_LS 0x3E8
|
|
#define STMMAC_DEFAULT_TWT_LS 0x1E
|
|
#define STMMAC_ET_MAX 0xFFFFF
|
|
|
|
#define STMMAC_CHAIN_MODE 0x1
|
|
#define STMMAC_RING_MODE 0x2
|
|
|
|
#define JUMBO_LEN 9000
|
|
|
|
/* Receive Side Scaling */
|
|
#define STMMAC_RSS_HASH_KEY_SIZE 40
|
|
#define STMMAC_RSS_MAX_TABLE_SIZE 256
|
|
|
|
/* VLAN */
|
|
#define STMMAC_VLAN_NONE 0x0
|
|
#define STMMAC_VLAN_REMOVE 0x1
|
|
#define STMMAC_VLAN_INSERT 0x2
|
|
#define STMMAC_VLAN_REPLACE 0x3
|
|
|
|
extern const struct stmmac_desc_ops enh_desc_ops;
|
|
extern const struct stmmac_desc_ops ndesc_ops;
|
|
|
|
struct mac_device_info;
|
|
|
|
extern const struct stmmac_hwtimestamp stmmac_ptp;
|
|
extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
|
|
|
|
struct mac_link {
|
|
u32 caps;
|
|
u32 speed_mask;
|
|
u32 speed10;
|
|
u32 speed100;
|
|
u32 speed1000;
|
|
u32 speed2500;
|
|
u32 duplex;
|
|
struct {
|
|
u32 speed2500;
|
|
u32 speed5000;
|
|
u32 speed10000;
|
|
} xgmii;
|
|
struct {
|
|
u32 speed25000;
|
|
u32 speed40000;
|
|
u32 speed50000;
|
|
u32 speed100000;
|
|
} xlgmii;
|
|
};
|
|
|
|
struct mii_regs {
|
|
unsigned int addr; /* MII Address */
|
|
unsigned int data; /* MII Data */
|
|
unsigned int addr_shift; /* MII address shift */
|
|
unsigned int reg_shift; /* MII reg shift */
|
|
unsigned int addr_mask; /* MII address mask */
|
|
unsigned int reg_mask; /* MII reg mask */
|
|
unsigned int clk_csr_shift;
|
|
unsigned int clk_csr_mask;
|
|
};
|
|
|
|
struct mac_device_info {
|
|
const struct stmmac_ops *mac;
|
|
const struct stmmac_desc_ops *desc;
|
|
const struct stmmac_dma_ops *dma;
|
|
const struct stmmac_mode_ops *mode;
|
|
const struct stmmac_hwtimestamp *ptp;
|
|
const struct stmmac_tc_ops *tc;
|
|
const struct stmmac_mmc_ops *mmc;
|
|
const struct stmmac_est_ops *est;
|
|
struct dw_xpcs *xpcs;
|
|
struct phylink_pcs *phylink_pcs;
|
|
struct mii_regs mii; /* MII register Addresses */
|
|
struct mac_link link;
|
|
void __iomem *pcsr; /* vpointer to device CSRs */
|
|
unsigned int multicast_filter_bins;
|
|
unsigned int unicast_filter_entries;
|
|
unsigned int mcast_bits_log2;
|
|
unsigned int rx_csum;
|
|
unsigned int pcs;
|
|
unsigned int pmt;
|
|
unsigned int ps;
|
|
unsigned int xlgmac;
|
|
unsigned int num_vlan;
|
|
u32 vlan_filter[32];
|
|
bool vlan_fail_q_en;
|
|
u8 vlan_fail_q;
|
|
bool hw_vlan_en;
|
|
};
|
|
|
|
struct stmmac_rx_routing {
|
|
u32 reg_mask;
|
|
u32 reg_shift;
|
|
};
|
|
|
|
int dwmac100_setup(struct stmmac_priv *priv);
|
|
int dwmac1000_setup(struct stmmac_priv *priv);
|
|
int dwmac4_setup(struct stmmac_priv *priv);
|
|
int dwxgmac2_setup(struct stmmac_priv *priv);
|
|
int dwxlgmac2_setup(struct stmmac_priv *priv);
|
|
|
|
void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
|
|
unsigned int high, unsigned int low);
|
|
void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
|
|
unsigned int high, unsigned int low);
|
|
void stmmac_set_mac(void __iomem *ioaddr, bool enable);
|
|
|
|
void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
|
|
unsigned int high, unsigned int low);
|
|
void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
|
|
unsigned int high, unsigned int low);
|
|
void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
|
|
|
|
void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
|
|
|
|
extern const struct stmmac_mode_ops ring_mode_ops;
|
|
extern const struct stmmac_mode_ops chain_mode_ops;
|
|
extern const struct stmmac_desc_ops dwmac4_desc_ops;
|
|
|
|
#endif /* __COMMON_H__ */
|