119 lines
3.9 KiB
C
119 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2020 Intel Corporation. */
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#ifndef __CXL_CORE_H__
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#define __CXL_CORE_H__
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extern const struct device_type cxl_nvdimm_bridge_type;
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extern const struct device_type cxl_nvdimm_type;
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extern const struct device_type cxl_pmu_type;
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extern struct attribute_group cxl_base_attribute_group;
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#ifdef CONFIG_CXL_REGION
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extern struct device_attribute dev_attr_create_pmem_region;
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extern struct device_attribute dev_attr_create_ram_region;
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extern struct device_attribute dev_attr_delete_region;
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extern struct device_attribute dev_attr_region;
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extern const struct device_type cxl_pmem_region_type;
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extern const struct device_type cxl_dax_region_type;
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extern const struct device_type cxl_region_type;
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void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled);
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#define CXL_REGION_ATTR(x) (&dev_attr_##x.attr)
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#define CXL_REGION_TYPE(x) (&cxl_region_type)
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#define SET_CXL_REGION_ATTR(x) (&dev_attr_##x.attr),
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#define CXL_PMEM_REGION_TYPE(x) (&cxl_pmem_region_type)
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#define CXL_DAX_REGION_TYPE(x) (&cxl_dax_region_type)
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int cxl_region_init(void);
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void cxl_region_exit(void);
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int cxl_get_poison_by_endpoint(struct cxl_port *port);
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struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa);
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u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd,
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u64 dpa);
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#else
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static inline u64 cxl_dpa_to_hpa(struct cxl_region *cxlr,
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const struct cxl_memdev *cxlmd, u64 dpa)
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{
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return ULLONG_MAX;
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}
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static inline
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struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa)
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{
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return NULL;
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}
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static inline int cxl_get_poison_by_endpoint(struct cxl_port *port)
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{
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return 0;
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}
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static inline void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled)
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{
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}
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static inline int cxl_region_init(void)
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{
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return 0;
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}
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static inline void cxl_region_exit(void)
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{
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}
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#define CXL_REGION_ATTR(x) NULL
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#define CXL_REGION_TYPE(x) NULL
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#define SET_CXL_REGION_ATTR(x)
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#define CXL_PMEM_REGION_TYPE(x) NULL
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#define CXL_DAX_REGION_TYPE(x) NULL
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#endif
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struct cxl_send_command;
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struct cxl_mem_query_commands;
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int cxl_query_cmd(struct cxl_memdev *cxlmd,
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struct cxl_mem_query_commands __user *q);
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int cxl_send_cmd(struct cxl_memdev *cxlmd, struct cxl_send_command __user *s);
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void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
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resource_size_t length);
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struct dentry *cxl_debugfs_create_dir(const char *dir);
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int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled,
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enum cxl_decoder_mode mode);
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int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size);
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int cxl_dpa_free(struct cxl_endpoint_decoder *cxled);
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resource_size_t cxl_dpa_size(struct cxl_endpoint_decoder *cxled);
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resource_size_t cxl_dpa_resource_start(struct cxl_endpoint_decoder *cxled);
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enum cxl_rcrb {
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CXL_RCRB_DOWNSTREAM,
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CXL_RCRB_UPSTREAM,
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};
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struct cxl_rcrb_info;
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resource_size_t __rcrb_to_component(struct device *dev,
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struct cxl_rcrb_info *ri,
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enum cxl_rcrb which);
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u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb);
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#define PCI_RCRB_CAP_LIST_ID_MASK GENMASK(7, 0)
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#define PCI_RCRB_CAP_HDR_ID_MASK GENMASK(7, 0)
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#define PCI_RCRB_CAP_HDR_NEXT_MASK GENMASK(15, 8)
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#define PCI_CAP_EXP_SIZEOF 0x3c
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extern struct rw_semaphore cxl_dpa_rwsem;
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extern struct rw_semaphore cxl_region_rwsem;
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int cxl_memdev_init(void);
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void cxl_memdev_exit(void);
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void cxl_mbox_init(void);
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enum cxl_poison_trace_type {
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CXL_POISON_TRACE_LIST,
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CXL_POISON_TRACE_INJECT,
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CXL_POISON_TRACE_CLEAR,
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};
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long cxl_pci_get_latency(struct pci_dev *pdev);
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int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c);
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int cxl_update_hmat_access_coordinates(int nid, struct cxl_region *cxlr,
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enum access_coordinate_class access);
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bool cxl_need_node_perf_attrs_update(int nid);
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int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port,
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struct access_coordinate *c);
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#endif /* __CXL_CORE_H__ */
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