521 lines
12 KiB
Plaintext
521 lines
12 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Turris 1.x Device Tree Source
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*
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* Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/)
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*
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* Pinout, Schematics and Altium hardware design files are open source
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* and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/leds/common.h>
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/include/ "fsl/p2020si-pre.dtsi"
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/ {
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model = "Turris 1.x";
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compatible = "cznic,turris1x";
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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pci2 = &pci2;
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spi0 = &spi0;
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};
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memory {
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device_type = "memory";
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};
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soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x00100000>;
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i2c@3000 {
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/* PCA9557PW GPIO controller for boot config */
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gpio-controller@18 {
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compatible = "nxp,pca9557";
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label = "bootcfg";
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reg = <0x18>;
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#gpio-cells = <2>;
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gpio-controller;
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polarity = <0x00>;
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};
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/* STM32F030R8T6 MCU for power control */
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power-control@2a {
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/*
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* Turris Power Control firmware runs on STM32F0 MCU.
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* This firmware is open source and available at:
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* https://gitlab.nic.cz/turris/hw/turris_power_control
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*/
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reg = <0x2a>;
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};
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/* DDR3 SPD/EEPROM PSWP instruction */
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eeprom@32 {
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reg = <0x32>;
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};
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/* SA56004ED temperature control */
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temperature-sensor@4c {
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compatible = "nxp,sa56004";
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reg = <0x4c>;
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interrupt-parent = <&gpio>;
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interrupts = <12 IRQ_TYPE_LEVEL_LOW>, /* GPIO12 - ALERT pin */
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<13 IRQ_TYPE_LEVEL_LOW>; /* GPIO13 - CRIT pin */
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#address-cells = <1>;
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#size-cells = <0>;
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/* Local temperature sensor (SA56004ED internal) */
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channel@0 {
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reg = <0>;
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label = "board";
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};
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/* Remote temperature sensor (D+/D- connected to P2020 CPU Temperature Diode) */
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channel@1 {
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reg = <1>;
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label = "cpu";
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};
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};
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/* DDR3 SPD/EEPROM */
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eeprom@52 {
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compatible = "atmel,spd";
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reg = <0x52>;
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};
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/* MCP79402-I/ST Protected EEPROM */
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eeprom@57 {
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reg = <0x57>;
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};
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/* ATSHA204-TH-DA-T crypto module */
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crypto@64 {
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compatible = "atmel,atsha204";
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reg = <0x64>;
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};
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/* IDT6V49205BNLGI clock generator */
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clock-generator@69 {
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compatible = "idt,6v49205b";
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reg = <0x69>;
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};
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/* MCP79402-I/ST RTC */
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rtc@6f {
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compatible = "microchip,mcp7940x";
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reg = <0x6f>;
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interrupt-parent = <&gpio>;
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interrupts = <14 0>; /* GPIO14 - MFP pin */
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};
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};
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/* SPI on connector P1 */
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spi0: spi@7000 {
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};
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gpio: gpio-controller@fc00 {
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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/* Connected to SMSC USB2412-DZK 2-Port USB 2.0 Hub Controller */
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usb@22000 {
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phy_type = "ulpi";
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dr_mode = "host";
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};
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enet0: ethernet@24000 {
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/* Connected to port 6 of QCA8337N-AL3C switch */
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phy-connection-type = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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mdio@24520 {
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/* KSZ9031RNXCA ethernet phy for WAN port */
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phy: ethernet-phy@7 {
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interrupts = <3 1 0 0>;
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reg = <0x7>;
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};
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/* QCA8337N-AL3C switch with integrated ethernet PHYs for LAN ports */
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switch@10 {
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compatible = "qca,qca8337";
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interrupts = <2 1 0 0>;
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reg = <0x10>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "cpu";
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ethernet = <&enet1>;
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phy-mode = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@1 {
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reg = <1>;
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label = "lan5";
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};
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port@2 {
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reg = <2>;
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label = "lan4";
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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};
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port@4 {
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reg = <4>;
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label = "lan2";
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};
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port@5 {
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reg = <5>;
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label = "lan1";
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&enet0>;
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phy-mode = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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ptp_clock@24e00 {
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fsl,tclk-period = <5>;
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fsl,tmr-prsc = <200>;
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fsl,tmr-add = <0xcccccccd>;
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fsl,tmr-fiper1 = <0x3b9ac9fb>;
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fsl,tmr-fiper2 = <0x0001869b>;
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fsl,max-adj = <249999999>;
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};
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enet1: ethernet@25000 {
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/* Connected to port 0 of QCA8337N-AL3C switch */
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phy-connection-type = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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mdio@25520 {
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status = "disabled";
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};
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enet2: ethernet@26000 {
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/* Connected to KSZ9031RNXCA ethernet phy (WAN port) */
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label = "wan";
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phy-handle = <&phy>;
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phy-connection-type = "rgmii-id";
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};
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mdio@26520 {
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status = "disabled";
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};
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sdhc@2e000 {
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bus-width = <4>;
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cd-gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
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};
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};
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lbc: localbus@ffe05000 {
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reg = <0 0xffe05000 0 0x1000>;
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ranges = <0x0 0x0 0x0 0xef000000 0x01000000>, /* NOR */
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<0x1 0x0 0x0 0xff800000 0x00040000>, /* NAND */
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<0x3 0x0 0x0 0xffa00000 0x00020000>; /* CPLD */
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/* S29GL128P90TFIR10 NOR */
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nor@0,0 {
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x01000000>;
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bank-width = <2>;
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device-width = <1>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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/* 128 kB for Device Tree Blob */
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reg = <0x00000000 0x00020000>;
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label = "dtb";
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};
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partition@20000 {
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/* 1.7 MB for Linux Kernel Image */
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reg = <0x00020000 0x001a0000>;
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label = "kernel";
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};
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partition@1c0000 {
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/* 1.5 MB for Rescue JFFS2 Root File System */
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reg = <0x001c0000 0x00180000>;
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label = "rescue";
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};
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partition@340000 {
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/* 11 MB for TAR.XZ Archive with Factory content of NAND Root File System */
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reg = <0x00340000 0x00b00000>;
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label = "factory";
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};
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partition@e40000 {
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/* 768 kB for Certificates JFFS2 File System */
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reg = <0x00e40000 0x000c0000>;
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label = "certificates";
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};
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/* free unused space 0x00f00000-0x00f20000 */
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partition@f20000 {
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/* 128 kB for U-Boot Environment Variables */
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reg = <0x00f20000 0x00020000>;
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label = "u-boot-env";
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};
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partition@f40000 {
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/* 768 kB for U-Boot Bootloader Image */
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reg = <0x00f40000 0x000c0000>;
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label = "u-boot";
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};
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};
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};
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/* MT29F2G08ABAEAWP:E NAND */
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nand@1,0 {
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compatible = "fsl,p2020-fcm-nand", "fsl,elbc-fcm-nand";
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reg = <0x1 0x0 0x00040000>;
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nand-ecc-mode = "soft";
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nand-ecc-algo = "bch";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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/* 256 MB for UBI with one volume: UBIFS Root File System */
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reg = <0x00000000 0x10000000>;
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label = "rootfs";
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};
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};
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};
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/* LCMXO1200C-3FTN256C FPGA */
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cpld@3,0 {
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/*
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* Turris CPLD firmware which runs on this Lattice FPGA,
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* is extended version of P1021RDB-PC CPLD v4.1 firmware.
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* It is backward compatible with its original version
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* and the only extension is support for Turris LEDs.
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* Turris CPLD firmware is open source and available at:
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* https://gitlab.nic.cz/turris/hw/turris_cpld/-/blob/master/CZ_NIC_Router_CPLD.v
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*/
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compatible = "cznic,turris1x-cpld", "fsl,p1021rdb-pc-cpld", "simple-bus", "syscon";
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reg = <0x3 0x0 0x30>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x3 0x0 0x00020000>;
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/* MAX6370KA+T watchdog */
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watchdog@2 {
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/*
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* CPLD firmware maps SET0, SET1 and SET2
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* input logic of MAX6370KA+T chip to CPLD
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* memory space at byte offset 0x2. WDI
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* input logic is outside of the CPLD and
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* connected via external GPIO.
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*/
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compatible = "maxim,max6370";
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reg = <0x02 0x01>;
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gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
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};
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reboot@d {
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/*
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* CPLD firmware which manages system reset and
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* watchdog registers has bugs. It does not
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* autoclear system reset register after change
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* and watchdog ignores reset line on immediate
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* succeeding reset cycle triggered by watchdog.
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* These bugs have to be workarounded in U-Boot
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* bootloader. So use system reset via syscon as
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* a last resort because older U-Boot versions
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* do not have workaround for watchdog.
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*
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* Reset method via rstcr's global-utilities
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* (the preferred one) has priority level 128,
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* watchdog has priority level 0 and default
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* syscon-reboot priority level is 192.
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*
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* So define syscon-reboot with custom priority
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* level 64 (between rstcr and watchdog) because
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* rstcr should stay as default preferred reset
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* method and reset via watchdog is more broken
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* than system reset via syscon.
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*/
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compatible = "syscon-reboot";
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reg = <0x0d 0x01>;
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offset = <0x0d>;
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mask = <0x01>;
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value = <0x01>;
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priority = <64>;
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};
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led-controller@13 {
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/*
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* LEDs are controlled by CPLD firmware.
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* All five LAN LEDs share common RGB settings
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* and so it is not possible to set different
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* colors on different LAN ports.
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*/
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compatible = "cznic,turris1x-leds";
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reg = <0x13 0x1d>;
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#address-cells = <1>;
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#size-cells = <0>;
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multi-led@0 {
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reg = <0x0>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_WAN;
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};
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multi-led@1 {
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reg = <0x1>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <5>;
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};
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multi-led@2 {
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reg = <0x2>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <4>;
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};
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multi-led@3 {
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reg = <0x3>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <3>;
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};
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multi-led@4 {
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reg = <0x4>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <2>;
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};
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multi-led@5 {
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reg = <0x5>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <1>;
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};
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multi-led@6 {
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reg = <0x6>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_WLAN;
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};
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multi-led@7 {
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reg = <0x7>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_POWER;
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};
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};
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};
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};
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pci2: pcie@ffe08000 {
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/*
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* PCIe bus for on-board TUSB7340RKM USB 3.0 xHCI controller.
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* This xHCI controller is available only on Turris 1.1 boards.
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* Turris 1.0 boards have nothing connected to this PCIe bus,
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* so system would see only PCIe Root Port of this PCIe Root
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* Complex. TUSB7340RKM xHCI controller has four SuperSpeed
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* channels. Channel 0 is connected to the front USB 3.0 port,
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* channel 1 (but only USB 2.0 subset) to USB 2.0 pins on mPCIe
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* slot 1 (CN5), channels 2 and 3 to connector P600.
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*
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* P2020 PCIe Root Port does not use PCIe MEM and xHCI controller
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* uses 64kB + 8kB of PCIe MEM. No PCIe IO is used or required.
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* So allocate 128kB of PCIe MEM for this PCIe bus.
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*/
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reg = <0 0xffe08000 0 0x1000>;
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ranges = <0x02000000 0x0 0xc0000000 0 0xc0000000 0x0 0x00020000>, /* MEM */
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<0x01000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>; /* IO */
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pcie@0 {
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ranges;
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};
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};
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pci1: pcie@ffe09000 {
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/* PCIe bus on mPCIe slot 2 (CN6) for expansion mPCIe card */
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reg = <0 0xffe09000 0 0x1000>;
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ranges = <0x02000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000>, /* MEM */
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<0x01000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>; /* IO */
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pcie@0 {
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ranges;
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};
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};
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pci0: pcie@ffe0a000 {
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/*
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* PCIe bus on mPCIe slot 1 (CN5) for expansion mPCIe card.
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* Turris 1.1 boards have in this mPCIe slot additional USB 2.0
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* pins via channel 1 of TUSB7340RKM xHCI controller and also
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* additional SIM card slot, both for USB-based WWAN cards.
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*/
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reg = <0 0xffe0a000 0 0x1000>;
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ranges = <0x02000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000>, /* MEM */
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<0x01000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>; /* IO */
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pcie@0 {
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ranges;
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};
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};
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};
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/include/ "fsl/p2020si-post.dtsi"
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