243 lines
		
	
	
		
			7.3 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			243 lines
		
	
	
		
			7.3 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| /*
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|  * Device Tree Source for IBM Embedded PPC 476 Platform
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|  *
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|  * Copyright © 2011 Tony Breeds IBM Corporation
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|  *
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|  * This file is licensed under the terms of the GNU General Public
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|  * License version 2.  This program is licensed "as is" without
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|  * any warranty of any kind, whether express or implied.
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|  */
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| 
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| /dts-v1/;
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| 
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| /memreserve/ 0x01f00000 0x00100000;	// spin table
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| 
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| / {
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| 	#address-cells = <2>;
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| 	#size-cells = <2>;
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| 	model = "ibm,currituck";
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| 	compatible = "ibm,currituck";
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| 	dcr-parent = <&{/cpus/cpu@0}>;
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| 
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| 	aliases {
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| 		serial0 = &UART0;
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| 	};
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| 
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| 	cpus {
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| 		#address-cells = <1>;
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| 		#size-cells = <0>;
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| 
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| 		cpu@0 {
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| 			device_type = "cpu";
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| 			model = "PowerPC,476";
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| 			reg = <0>;
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| 			clock-frequency = <1600000000>; // 1.6 GHz
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| 			timebase-frequency = <100000000>; // 100Mhz
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| 			i-cache-line-size = <32>;
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| 			d-cache-line-size = <32>;
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| 			i-cache-size = <32768>;
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| 			d-cache-size = <32768>;
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| 			dcr-controller;
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| 			dcr-access-method = "native";
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| 			status = "okay";
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| 		};
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| 		cpu@1 {
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| 			device_type = "cpu";
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| 			model = "PowerPC,476";
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| 			reg = <1>;
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| 			clock-frequency = <1600000000>; // 1.6 GHz
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| 			timebase-frequency = <100000000>; // 100Mhz
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| 			i-cache-line-size = <32>;
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| 			d-cache-line-size = <32>;
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| 			i-cache-size = <32768>;
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| 			d-cache-size = <32768>;
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| 			dcr-controller;
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| 			dcr-access-method = "native";
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| 			status = "disabled";
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| 			enable-method = "spin-table";
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| 			cpu-release-addr = <0x0 0x01f00000>;
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| 		};
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| 	};
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| 
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| 	memory {
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| 		device_type = "memory";
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| 		reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
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| 	};
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| 
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| 	MPIC: interrupt-controller {
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| 		compatible = "chrp,open-pic";
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| 		interrupt-controller;
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| 		dcr-reg = <0xffc00000 0x00040000>;
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| 		#address-cells = <0>;
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| 		#size-cells = <0>;
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| 		#interrupt-cells = <2>;
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| 
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| 	};
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| 
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| 	plb {
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| 		compatible = "ibm,plb6";
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| 		#address-cells = <2>;
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| 		#size-cells = <2>;
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| 		ranges;
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| 		clock-frequency = <200000000>; // 200Mhz
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| 
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| 		POB0: opb {
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| 			compatible = "ibm,opb-4xx", "ibm,opb";
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| 			#address-cells = <1>;
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| 			#size-cells = <1>;
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| 			/* Wish there was a nicer way of specifying a full
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| 			 * 32-bit range
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| 			 */
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| 			ranges = <0x00000000 0x00000200 0x00000000 0x80000000
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| 				  0x80000000 0x00000200 0x80000000 0x80000000>;
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| 			clock-frequency = <100000000>;
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| 
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| 			UART0: serial@10000000 {
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| 				device_type = "serial";
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| 				compatible = "ns16750", "ns16550";
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| 				reg = <0x10000000 0x00000008>;
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| 				virtual-reg = <0xe1000000>;
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| 				clock-frequency = <1851851>; // PCIe refclk/MCGC0_CTL[UART]
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| 				current-speed = <115200>;
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| 				interrupt-parent = <&MPIC>;
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| 				interrupts = <34 2>;
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| 			};
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| 
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| 			FPGA0: fpga@50000000 {
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| 				compatible = "ibm,currituck-fpga";
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| 				reg = <0x50000000 0x4>;
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| 			};
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| 
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| 			IIC0: i2c@0 {
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| 				compatible = "ibm,iic-currituck", "ibm,iic";
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| 				reg = <0x0 0x00000014>;
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| 				interrupt-parent = <&MPIC>;
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| 				interrupts = <79 2>;
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| 				#address-cells = <1>;
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| 				#size-cells = <0>;
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|                                 rtc@68 {
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|                                         compatible = "st,m41t80", "m41st85";
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|                                         reg = <0x68>;
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|                                 };
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| 			};
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| 		};
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| 
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| 		PCIE0: pcie@10100000000 {		// 4xGBIF1
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| 			device_type = "pci";
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| 			#interrupt-cells = <1>;
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| 			#size-cells = <2>;
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| 			#address-cells = <3>;
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| 			compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
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| 			primary;
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| 			port = <0x0>; /* port number */
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| 			reg = <0x00000101 0x00000000 0x0 0x10000000		/* Config space access */
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| 			       0x00000100 0x00000000 0x0 0x00001000>;	/* UTL Registers space access */
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| 			dcr-reg = <0x80 0x20>;
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| 
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| //                                pci_space  < pci_addr          > < cpu_addr          > < size       >
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| 			ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
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| 			          0x01000000 0x0        0x0        0x00000140 0x0        0x0 0x00010000>;
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| 
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| 			/* Inbound starting at 0 to memsize filled in by zImage */
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| 			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
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| 
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| 			/* This drives busses 0 to 0xf */
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| 			bus-range = <0x0 0xf>;
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| 
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| 			/* Legacy interrupts (note the weird polarity, the bridge seems
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| 			 * to invert PCIe legacy interrupts).
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| 			 * We are de-swizzling here because the numbers are actually for
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| 			 * port of the root complex virtual P2P bridge. But I want
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| 			 * to avoid putting a node for it in the tree, so the numbers
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| 			 * below are basically de-swizzled numbers.
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| 			 * The real slot is on idsel 0, so the swizzling is 1:1
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| 			 */
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| 			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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| 			interrupt-map = <
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| 				0x0 0x0 0x0 0x1 &MPIC 46 0x2 /* int A */
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| 				0x0 0x0 0x0 0x2 &MPIC 47 0x2 /* int B */
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| 				0x0 0x0 0x0 0x3 &MPIC 48 0x2 /* int C */
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| 				0x0 0x0 0x0 0x4 &MPIC 49 0x2 /* int D */>;
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| 		};
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| 
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| 		PCIE1: pcie@30100000000 {		// 4xGBIF0
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| 			device_type = "pci";
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| 			#interrupt-cells = <1>;
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| 			#size-cells = <2>;
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| 			#address-cells = <3>;
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| 			compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
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| 			primary;
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| 			port = <0x1>; /* port number */
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| 			reg = <0x00000301 0x00000000 0x0 0x10000000		/* Config space access */
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| 			       0x00000300 0x00000000 0x0 0x00001000>;	/* UTL Registers space access */
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| 			dcr-reg = <0x60 0x20>;
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| 
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| 			ranges = <0x02000000 0x00000000 0x80000000 0x00000310 0x80000000 0x0 0x80000000
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| 			          0x01000000 0x0        0x0        0x00000340 0x0        0x0 0x00010000>;
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| 
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| 			/* Inbound starting at 0 to memsize filled in by zImage */
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| 			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
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| 
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| 			/* This drives busses 0 to 0xf */
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| 			bus-range = <0x0 0xf>;
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| 
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| 			/* Legacy interrupts (note the weird polarity, the bridge seems
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| 			 * to invert PCIe legacy interrupts).
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| 			 * We are de-swizzling here because the numbers are actually for
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| 			 * port of the root complex virtual P2P bridge. But I want
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| 			 * to avoid putting a node for it in the tree, so the numbers
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| 			 * below are basically de-swizzled numbers.
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| 			 * The real slot is on idsel 0, so the swizzling is 1:1
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| 			 */
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| 			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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| 			interrupt-map = <
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| 				0x0 0x0 0x0 0x1 &MPIC 38 0x2 /* int A */
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| 				0x0 0x0 0x0 0x2 &MPIC 39 0x2 /* int B */
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| 				0x0 0x0 0x0 0x3 &MPIC 40 0x2 /* int C */
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| 				0x0 0x0 0x0 0x4 &MPIC 41 0x2 /* int D */>;
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| 		};
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| 
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| 		PCIE2: pcie@38100000000 {		// 2xGBIF0
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| 			device_type = "pci";
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| 			#interrupt-cells = <1>;
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| 			#size-cells = <2>;
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| 			#address-cells = <3>;
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| 			compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
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| 			primary;
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| 			port = <0x2>; /* port number */
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| 			reg = <0x00000381 0x00000000 0x0 0x10000000		/* Config space access */
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| 			       0x00000380 0x00000000 0x0 0x00001000>;	/* UTL Registers space access */
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| 			dcr-reg = <0xA0 0x20>;
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| 
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| 			ranges = <0x02000000 0x00000000 0x80000000 0x00000390 0x80000000 0x0 0x80000000
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| 			          0x01000000 0x0        0x0        0x000003C0 0x0        0x0 0x00010000>;
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| 
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| 			/* Inbound starting at 0 to memsize filled in by zImage */
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| 			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
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| 
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| 			/* This drives busses 0 to 0xf */
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| 			bus-range = <0x0 0xf>;
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| 
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| 			/* Legacy interrupts (note the weird polarity, the bridge seems
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| 			 * to invert PCIe legacy interrupts).
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| 			 * We are de-swizzling here because the numbers are actually for
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| 			 * port of the root complex virtual P2P bridge. But I want
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| 			 * to avoid putting a node for it in the tree, so the numbers
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| 			 * below are basically de-swizzled numbers.
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| 			 * The real slot is on idsel 0, so the swizzling is 1:1
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| 			 */
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| 			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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| 			interrupt-map = <
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| 				0x0 0x0 0x0 0x1 &MPIC 54 0x2 /* int A */
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| 				0x0 0x0 0x0 0x2 &MPIC 55 0x2 /* int B */
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| 				0x0 0x0 0x0 0x3 &MPIC 56 0x2 /* int C */
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| 				0x0 0x0 0x0 0x4 &MPIC 57 0x2 /* int D */>;
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| 		};
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| 
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| 	};
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| 
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| 	chosen {
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| 		stdout-path = &UART0;
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| 	};
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| };
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