40 lines
1.5 KiB
Plaintext
40 lines
1.5 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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# common clock support for SOPHGO SoC family.
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config CLK_SOPHGO_CV1800
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tristate "Support for the Sophgo CV1800 series SoCs clock controller"
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depends on ARCH_SOPHGO || COMPILE_TEST
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help
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This driver supports clock controller of Sophgo CV18XX series SoC.
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The driver require a 25MHz Oscillator to function generate clock.
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It includes PLLs, common clock function and some vendor clock for
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IPs of CV18XX series SoC
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config CLK_SOPHGO_SG2042_PLL
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tristate "Sophgo SG2042 PLL clock support"
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depends on ARCH_SOPHGO || COMPILE_TEST
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help
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This driver supports the PLL clock controller on the
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Sophgo SG2042 SoC. This clock IP uses three oscillators with
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frequency of 25 MHz as input, which are used for Main/Fixed
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PLL, DDR PLL 0 and DDR PLL 1 respectively.
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config CLK_SOPHGO_SG2042_CLKGEN
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tristate "Sophgo SG2042 Clock Generator support"
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depends on CLK_SOPHGO_SG2042_PLL
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help
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This driver supports the Clock Generator on the
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Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock
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because it uses PLL clocks as input.
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This driver provides clock function such as DIV/Mux/Gate.
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config CLK_SOPHGO_SG2042_RPGATE
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tristate "Sophgo SG2042 RP subsystem clock controller support"
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depends on CLK_SOPHGO_SG2042_CLKGEN
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help
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This driver supports the RP((Riscv Processors)) subsystem clock
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controller on the Sophgo SG2042 SoC.
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This clock IP depends on SG2042 Clock Generator because it uses
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clock from Clock Generator IP as input.
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This driver provides Gate function for RP.
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