91 lines
1.8 KiB
YAML
91 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/nvidia,tegra20-slink.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra20/30 SLINK controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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enum:
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- nvidia,tegra20-slink
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- nvidia,tegra30-slink
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: module clock
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resets:
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items:
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- description: module reset
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reset-names:
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items:
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- const: spi
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dmas:
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items:
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- description: DMA channel used for reception
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- description: DMA channel used for transmission
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dma-names:
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items:
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- const: rx
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- const: tx
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operating-points-v2:
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$ref: /schemas/types.yaml#/definitions/phandle
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power-domains:
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items:
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- description: phandle to the core power domain
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spi-max-frequency:
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description: Maximum SPI clocking speed of the controller in Hz.
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$ref: /schemas/types.yaml#/definitions/uint32
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allOf:
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- $ref: spi-controller.yaml
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- resets
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- reset-names
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- dmas
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- dma-names
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examples:
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- |
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#include <dt-bindings/clock/tegra20-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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spi@7000d600 {
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compatible = "nvidia,tegra20-slink";
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reg = <0x7000d600 0x200>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <25000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA20_CLK_SBC2>;
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resets = <&tegra_car 44>;
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reset-names = "spi";
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dmas = <&apbdma 16>, <&apbdma 16>;
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dma-names = "rx", "tx";
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};
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