89 lines
		
	
	
		
			2.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			89 lines
		
	
	
		
			2.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0
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| /***************************************************************************/
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| 
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| /*
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|  *	525x.c  -- platform support for ColdFire 525x based boards
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|  *
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|  *	Copyright (C) 2012, Steven King <sfking@fdwdc.com>
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|  */
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| 
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| /***************************************************************************/
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| 
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| #include <linux/clkdev.h>
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| #include <linux/kernel.h>
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| #include <linux/param.h>
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| #include <linux/init.h>
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| #include <linux/io.h>
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| #include <linux/platform_device.h>
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| #include <asm/machdep.h>
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| #include <asm/coldfire.h>
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| #include <asm/mcfsim.h>
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| #include <asm/mcfclk.h>
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| 
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| /***************************************************************************/
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| 
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| DEFINE_CLK(pll, "pll.0", MCF_CLK);
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| DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
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| 
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| static struct clk_lookup m525x_clk_lookup[] = {
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| 	CLKDEV_INIT(NULL, "pll.0", &clk_pll),
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| 	CLKDEV_INIT(NULL, "sys.0", &clk_sys),
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| 	CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
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| 	CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
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| 	CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
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| 	CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
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| 	CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
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| 	CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
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| 	CLKDEV_INIT("imx1-i2c.1", NULL, &clk_sys),
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| };
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| 
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| /***************************************************************************/
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| 
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| static void __init m525x_qspi_init(void)
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| {
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| #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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| 	/* set the GPIO function for the qspi cs gpios */
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| 	/* FIXME: replace with pinmux/pinctl support */
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| 	u32 f = readl(MCFSIM2_GPIOFUNC);
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| 	f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
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| 	writel(f, MCFSIM2_GPIOFUNC);
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| 
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| 	/* QSPI irq setup */
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| 	writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
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| 	       MCFSIM_QSPIICR);
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| 	mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
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| #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
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| }
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| 
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| static void __init m525x_i2c_init(void)
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| {
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| #if IS_ENABLED(CONFIG_I2C_IMX)
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| 	u32 r;
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| 
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| 	/* first I2C controller uses regular irq setup */
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| 	writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
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| 	       MCFSIM_I2CICR);
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| 	mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
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| 
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| 	/* second I2C controller is completely different */
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| 	r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
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| 	r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
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| 	r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
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| 	writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
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| #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
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| }
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| 
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| /***************************************************************************/
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| 
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| void __init config_BSP(char *commandp, int size)
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| {
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| 	mach_sched_init = hw_timer_init;
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| 
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| 	m525x_qspi_init();
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| 	m525x_i2c_init();
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| 
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| 	clkdev_add_table(m525x_clk_lookup, ARRAY_SIZE(m525x_clk_lookup));
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| }
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| 
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| /***************************************************************************/
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