102 lines
2.3 KiB
C
102 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 1993 Hamish Macdonald
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* Copyright (C) 1999 D. Jeff Dionne
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* Copyright (C) 2001 Georges Menie, Ken Desmet
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <asm/machdep.h>
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#include <asm/MC68VZ328.h>
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#include "screen.h"
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/***************************************************************************/
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/* Init Drangon Engine hardware */
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/***************************************************************************/
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static void dragen2_reset(void)
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{
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local_irq_disable();
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#ifdef CONFIG_INIT_LCD
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PBDATA |= 0x20; /* disable CCFL light */
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PKDATA |= 0x4; /* disable LCD controller */
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LCKCON = 0;
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#endif
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__asm__ __volatile__(
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"reset\n\t"
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"moveal #0x04000000, %a0\n\t"
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"moveal 0(%a0), %sp\n\t"
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"moveal 4(%a0), %a0\n\t"
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"jmp (%a0)"
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);
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}
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void __init init_dragen2(char *command, int size)
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{
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mach_reset = dragen2_reset;
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#ifdef CONFIG_DIRECT_IO_ACCESS
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SCR = 0x10; /* allow user access to internal registers */
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#endif
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/* CSGB Init */
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CSGBB = 0x4000;
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CSB = 0x1a1;
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/* CS8900 init */
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/* PK3: hardware sleep function pin, active low */
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PKSEL |= PK(3); /* select pin as I/O */
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PKDIR |= PK(3); /* select pin as output */
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PKDATA |= PK(3); /* set pin high */
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/* PF5: hardware reset function pin, active high */
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PFSEL |= PF(5); /* select pin as I/O */
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PFDIR |= PF(5); /* select pin as output */
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PFDATA &= ~PF(5); /* set pin low */
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/* cs8900 hardware reset */
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PFDATA |= PF(5);
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{ int i; for (i = 0; i < 32000; ++i); }
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PFDATA &= ~PF(5);
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/* INT1 enable (cs8900 IRQ) */
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PDPOL &= ~PD(1); /* active high signal */
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PDIQEG &= ~PD(1);
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PDIRQEN |= PD(1); /* IRQ enabled */
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#ifdef CONFIG_INIT_LCD
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/* initialize LCD controller */
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LSSA = (long) screen_bits;
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LVPW = 0x14;
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LXMAX = 0x140;
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LYMAX = 0xef;
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LRRA = 0;
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LPXCD = 3;
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LPICF = 0x08;
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LPOLCF = 0;
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LCKCON = 0x80;
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PCPDEN = 0xff;
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PCSEL = 0;
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/* Enable LCD controller */
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PKDIR |= 0x4;
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PKSEL |= 0x4;
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PKDATA &= ~0x4;
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/* Enable CCFL backlighting circuit */
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PBDIR |= 0x20;
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PBSEL |= 0x20;
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PBDATA &= ~0x20;
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/* contrast control register */
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PFDIR |= 0x1;
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PFSEL &= ~0x1;
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PWMR = 0x037F;
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#endif
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}
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