195 lines
8.5 KiB
ReStructuredText
195 lines
8.5 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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PXA-Camera Host Driver
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======================
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Author: Robert Jarzmik <robert.jarzmik@free.fr>
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Constraints
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-----------
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a) Image size for YUV422P format
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All YUV422P images are enforced to have width x height % 16 = 0.
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This is due to DMA constraints, which transfers only planes of 8 byte
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multiples.
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Global video workflow
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---------------------
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a) QCI stopped
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Initially, the QCI interface is stopped.
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When a buffer is queued (pxa_videobuf_ops->buf_queue), the QCI starts.
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b) QCI started
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More buffers can be queued while the QCI is started without halting the
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capture. The new buffers are "appended" at the tail of the DMA chain, and
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smoothly captured one frame after the other.
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Once a buffer is filled in the QCI interface, it is marked as "DONE" and
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removed from the active buffers list. It can be then requeud or dequeued by
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userland application.
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Once the last buffer is filled in, the QCI interface stops.
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c) Capture global finite state machine schema
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.. code-block:: none
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+----+ +---+ +----+
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| DQ | | Q | | DQ |
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| v | v | v
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+-----------+ +------------------------+
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| STOP | | Wait for capture start |
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+-----------+ Q +------------------------+
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+-> | QCI: stop | ------------------> | QCI: run | <------------+
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| | DMA: stop | | DMA: stop | |
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| +-----------+ +-----> +------------------------+ |
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| / | |
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| / +---+ +----+ | |
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|capture list empty / | Q | | DQ | | QCI Irq EOF |
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| / | v | v v |
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| +--------------------+ +----------------------+ |
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| | DMA hotlink missed | | Capture running | |
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| +--------------------+ +----------------------+ |
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| | QCI: run | +-----> | QCI: run | <-+ |
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| | DMA: stop | / | DMA: run | | |
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| +--------------------+ / +----------------------+ | Other |
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| ^ /DMA still | | channels |
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| | capture list / running | DMA Irq End | not |
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| | not empty / | | finished |
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| | / v | yet |
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| +----------------------+ +----------------------+ | |
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| | Videobuf released | | Channel completed | | |
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| +----------------------+ +----------------------+ | |
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+-- | QCI: run | | QCI: run | --+ |
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| DMA: run | | DMA: run | |
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+----------------------+ +----------------------+ |
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^ / | |
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| no overrun / | overrun |
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| / v |
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+--------------------+ / +----------------------+ |
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| Frame completed | / | Frame overran | |
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+--------------------+ <-----+ +----------------------+ restart frame |
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| QCI: run | | QCI: stop | --------------+
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| DMA: run | | DMA: stop |
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+--------------------+ +----------------------+
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Legend: - each box is a FSM state
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- each arrow is the condition to transition to another state
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- an arrow with a comment is a mandatory transition (no condition)
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- arrow "Q" means : a buffer was enqueued
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- arrow "DQ" means : a buffer was dequeued
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- "QCI: stop" means the QCI interface is not enabled
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- "DMA: stop" means all 3 DMA channels are stopped
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- "DMA: run" means at least 1 DMA channel is still running
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DMA usage
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---------
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a) DMA flow
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- first buffer queued for capture
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Once a first buffer is queued for capture, the QCI is started, but data
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transfer is not started. On "End Of Frame" interrupt, the irq handler
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starts the DMA chain.
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- capture of one videobuffer
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The DMA chain starts transferring data into videobuffer RAM pages.
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When all pages are transferred, the DMA irq is raised on "ENDINTR" status
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- finishing one videobuffer
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The DMA irq handler marks the videobuffer as "done", and removes it from
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the active running queue
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Meanwhile, the next videobuffer (if there is one), is transferred by DMA
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- finishing the last videobuffer
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On the DMA irq of the last videobuffer, the QCI is stopped.
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b) DMA prepared buffer will have this structure
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.. code-block:: none
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+------------+-----+---------------+-----------------+
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| desc-sg[0] | ... | desc-sg[last] | finisher/linker |
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+------------+-----+---------------+-----------------+
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This structure is pointed by dma->sg_cpu.
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The descriptors are used as follows:
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- desc-sg[i]: i-th descriptor, transferring the i-th sg
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element to the video buffer scatter gather
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- finisher: has ddadr=DADDR_STOP, dcmd=ENDIRQEN
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- linker: has ddadr= desc-sg[0] of next video buffer, dcmd=0
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For the next schema, let's assume d0=desc-sg[0] .. dN=desc-sg[N],
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"f" stands for finisher and "l" for linker.
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A typical running chain is :
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.. code-block:: none
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Videobuffer 1 Videobuffer 2
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+---------+----+---+ +----+----+----+---+
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| d0 | .. | dN | l | | d0 | .. | dN | f |
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+---------+----+-|-+ ^----+----+----+---+
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+----+
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After the chaining is finished, the chain looks like :
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.. code-block:: none
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Videobuffer 1 Videobuffer 2 Videobuffer 3
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+---------+----+---+ +----+----+----+---+ +----+----+----+---+
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| d0 | .. | dN | l | | d0 | .. | dN | l | | d0 | .. | dN | f |
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+---------+----+-|-+ ^----+----+----+-|-+ ^----+----+----+---+
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| | | |
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+----+ +----+
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new_link
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c) DMA hot chaining timeslice issue
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As DMA chaining is done while DMA _is_ running, the linking may be done
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while the DMA jumps from one Videobuffer to another. On the schema, that
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would be a problem if the following sequence is encountered :
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- DMA chain is Videobuffer1 + Videobuffer2
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- pxa_videobuf_queue() is called to queue Videobuffer3
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- DMA controller finishes Videobuffer2, and DMA stops
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.. code-block:: none
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=>
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Videobuffer 1 Videobuffer 2
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+---------+----+---+ +----+----+----+---+
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| d0 | .. | dN | l | | d0 | .. | dN | f |
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+---------+----+-|-+ ^----+----+----+-^-+
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+----+ +-- DMA DDADR loads DDADR_STOP
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- pxa_dma_add_tail_buf() is called, the Videobuffer2 "finisher" is
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replaced by a "linker" to Videobuffer3 (creation of new_link)
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- pxa_videobuf_queue() finishes
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- the DMA irq handler is called, which terminates Videobuffer2
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- Videobuffer3 capture is not scheduled on DMA chain (as it stopped !!!)
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.. code-block:: none
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Videobuffer 1 Videobuffer 2 Videobuffer 3
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+---------+----+---+ +----+----+----+---+ +----+----+----+---+
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| d0 | .. | dN | l | | d0 | .. | dN | l | | d0 | .. | dN | f |
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+---------+----+-|-+ ^----+----+----+-|-+ ^----+----+----+---+
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| | | |
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+----+ +----+
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new_link
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DMA DDADR still is DDADR_STOP
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- pxa_camera_check_link_miss() is called
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This checks if the DMA is finished and a buffer is still on the
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pcdev->capture list. If that's the case, the capture will be restarted,
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and Videobuffer3 is scheduled on DMA chain.
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- the DMA irq handler finishes
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.. note::
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If DMA stops just after pxa_camera_check_link_miss() reads DDADR()
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value, we have the guarantee that the DMA irq handler will be called back
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when the DMA will finish the buffer, and pxa_camera_check_link_miss() will
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be called again, to reschedule Videobuffer3.
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