792 lines
33 KiB
ReStructuredText
792 lines
33 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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Spectre Side Channels
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=====================
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Spectre is a class of side channel attacks that exploit branch prediction
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and speculative execution on modern CPUs to read memory, possibly
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bypassing access controls. Speculative execution side channel exploits
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do not modify memory but attempt to infer privileged data in the memory.
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This document covers Spectre variant 1 and Spectre variant 2.
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Affected processors
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-------------------
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Speculative execution side channel methods affect a wide range of modern
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high performance processors, since most modern high speed processors
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use branch prediction and speculative execution.
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The following CPUs are vulnerable:
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- Intel Core, Atom, Pentium, and Xeon processors
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- AMD Phenom, EPYC, and Zen processors
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- IBM POWER and zSeries processors
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- Higher end ARM processors
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- Apple CPUs
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- Higher end MIPS CPUs
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- Likely most other high performance CPUs. Contact your CPU vendor for details.
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Whether a processor is affected or not can be read out from the Spectre
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vulnerability files in sysfs. See :ref:`spectre_sys_info`.
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Related CVEs
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------------
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The following CVE entries describe Spectre variants:
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============= ======================= ==========================
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CVE-2017-5753 Bounds check bypass Spectre variant 1
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CVE-2017-5715 Branch target injection Spectre variant 2
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CVE-2019-1125 Spectre v1 swapgs Spectre variant 1 (swapgs)
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============= ======================= ==========================
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Problem
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-------
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CPUs use speculative operations to improve performance. That may leave
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traces of memory accesses or computations in the processor's caches,
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buffers, and branch predictors. Malicious software may be able to
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influence the speculative execution paths, and then use the side effects
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of the speculative execution in the CPUs' caches and buffers to infer
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privileged data touched during the speculative execution.
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Spectre variant 1 attacks take advantage of speculative execution of
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conditional branches, while Spectre variant 2 attacks use speculative
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execution of indirect branches to leak privileged memory.
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See :ref:`[1] <spec_ref1>` :ref:`[5] <spec_ref5>` :ref:`[6] <spec_ref6>`
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:ref:`[7] <spec_ref7>` :ref:`[10] <spec_ref10>` :ref:`[11] <spec_ref11>`.
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Spectre variant 1 (Bounds Check Bypass)
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---------------------------------------
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The bounds check bypass attack :ref:`[2] <spec_ref2>` takes advantage
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of speculative execution that bypasses conditional branch instructions
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used for memory access bounds check (e.g. checking if the index of an
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array results in memory access within a valid range). This results in
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memory accesses to invalid memory (with out-of-bound index) that are
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done speculatively before validation checks resolve. Such speculative
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memory accesses can leave side effects, creating side channels which
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leak information to the attacker.
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There are some extensions of Spectre variant 1 attacks for reading data
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over the network, see :ref:`[12] <spec_ref12>`. However such attacks
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are difficult, low bandwidth, fragile, and are considered low risk.
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Note that, despite "Bounds Check Bypass" name, Spectre variant 1 is not
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only about user-controlled array bounds checks. It can affect any
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conditional checks. The kernel entry code interrupt, exception, and NMI
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handlers all have conditional swapgs checks. Those may be problematic
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in the context of Spectre v1, as kernel code can speculatively run with
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a user GS.
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Spectre variant 2 (Branch Target Injection)
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-------------------------------------------
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The branch target injection attack takes advantage of speculative
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execution of indirect branches :ref:`[3] <spec_ref3>`. The indirect
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branch predictors inside the processor used to guess the target of
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indirect branches can be influenced by an attacker, causing gadget code
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to be speculatively executed, thus exposing sensitive data touched by
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the victim. The side effects left in the CPU's caches during speculative
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execution can be measured to infer data values.
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.. _poison_btb:
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In Spectre variant 2 attacks, the attacker can steer speculative indirect
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branches in the victim to gadget code by poisoning the branch target
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buffer of a CPU used for predicting indirect branch addresses. Such
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poisoning could be done by indirect branching into existing code,
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with the address offset of the indirect branch under the attacker's
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control. Since the branch prediction on impacted hardware does not
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fully disambiguate branch address and uses the offset for prediction,
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this could cause privileged code's indirect branch to jump to a gadget
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code with the same offset.
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The most useful gadgets take an attacker-controlled input parameter (such
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as a register value) so that the memory read can be controlled. Gadgets
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without input parameters might be possible, but the attacker would have
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very little control over what memory can be read, reducing the risk of
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the attack revealing useful data.
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One other variant 2 attack vector is for the attacker to poison the
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return stack buffer (RSB) :ref:`[13] <spec_ref13>` to cause speculative
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subroutine return instruction execution to go to a gadget. An attacker's
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imbalanced subroutine call instructions might "poison" entries in the
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return stack buffer which are later consumed by a victim's subroutine
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return instructions. This attack can be mitigated by flushing the return
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stack buffer on context switch, or virtual machine (VM) exit.
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On systems with simultaneous multi-threading (SMT), attacks are possible
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from the sibling thread, as level 1 cache and branch target buffer
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(BTB) may be shared between hardware threads in a CPU core. A malicious
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program running on the sibling thread may influence its peer's BTB to
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steer its indirect branch speculations to gadget code, and measure the
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speculative execution's side effects left in level 1 cache to infer the
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victim's data.
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Yet another variant 2 attack vector is for the attacker to poison the
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Branch History Buffer (BHB) to speculatively steer an indirect branch
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to a specific Branch Target Buffer (BTB) entry, even if the entry isn't
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associated with the source address of the indirect branch. Specifically,
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the BHB might be shared across privilege levels even in the presence of
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Enhanced IBRS.
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Previously the only known real-world BHB attack vector was via unprivileged
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eBPF. Further research has found attacks that don't require unprivileged eBPF.
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For a full mitigation against BHB attacks it is recommended to set BHI_DIS_S or
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use the BHB clearing sequence.
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Attack scenarios
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----------------
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The following list of attack scenarios have been anticipated, but may
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not cover all possible attack vectors.
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1. A user process attacking the kernel
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Spectre variant 1
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~~~~~~~~~~~~~~~~~
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The attacker passes a parameter to the kernel via a register or
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via a known address in memory during a syscall. Such parameter may
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be used later by the kernel as an index to an array or to derive
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a pointer for a Spectre variant 1 attack. The index or pointer
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is invalid, but bound checks are bypassed in the code branch taken
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for speculative execution. This could cause privileged memory to be
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accessed and leaked.
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For kernel code that has been identified where data pointers could
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potentially be influenced for Spectre attacks, new "nospec" accessor
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macros are used to prevent speculative loading of data.
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Spectre variant 1 (swapgs)
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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An attacker can train the branch predictor to speculatively skip the
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swapgs path for an interrupt or exception. If they initialize
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the GS register to a user-space value, if the swapgs is speculatively
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skipped, subsequent GS-related percpu accesses in the speculation
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window will be done with the attacker-controlled GS value. This
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could cause privileged memory to be accessed and leaked.
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For example:
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::
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if (coming from user space)
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swapgs
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mov %gs:<percpu_offset>, %reg
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mov (%reg), %reg1
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When coming from user space, the CPU can speculatively skip the
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swapgs, and then do a speculative percpu load using the user GS
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value. So the user can speculatively force a read of any kernel
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value. If a gadget exists which uses the percpu value as an address
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in another load/store, then the contents of the kernel value may
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become visible via an L1 side channel attack.
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A similar attack exists when coming from kernel space. The CPU can
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speculatively do the swapgs, causing the user GS to get used for the
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rest of the speculative window.
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Spectre variant 2
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~~~~~~~~~~~~~~~~~
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A spectre variant 2 attacker can :ref:`poison <poison_btb>` the branch
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target buffer (BTB) before issuing syscall to launch an attack.
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After entering the kernel, the kernel could use the poisoned branch
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target buffer on indirect jump and jump to gadget code in speculative
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execution.
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If an attacker tries to control the memory addresses leaked during
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speculative execution, he would also need to pass a parameter to the
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gadget, either through a register or a known address in memory. After
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the gadget has executed, he can measure the side effect.
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The kernel can protect itself against consuming poisoned branch
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target buffer entries by using return trampolines (also known as
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"retpoline") :ref:`[3] <spec_ref3>` :ref:`[9] <spec_ref9>` for all
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indirect branches. Return trampolines trap speculative execution paths
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to prevent jumping to gadget code during speculative execution.
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x86 CPUs with Enhanced Indirect Branch Restricted Speculation
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(Enhanced IBRS) available in hardware should use the feature to
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mitigate Spectre variant 2 instead of retpoline. Enhanced IBRS is
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more efficient than retpoline.
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There may be gadget code in firmware which could be exploited with
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Spectre variant 2 attack by a rogue user process. To mitigate such
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attacks on x86, Indirect Branch Restricted Speculation (IBRS) feature
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is turned on before the kernel invokes any firmware code.
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2. A user process attacking another user process
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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A malicious user process can try to attack another user process,
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either via a context switch on the same hardware thread, or from the
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sibling hyperthread sharing a physical processor core on simultaneous
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multi-threading (SMT) system.
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Spectre variant 1 attacks generally require passing parameters
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between the processes, which needs a data passing relationship, such
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as remote procedure calls (RPC). Those parameters are used in gadget
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code to derive invalid data pointers accessing privileged memory in
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the attacked process.
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Spectre variant 2 attacks can be launched from a rogue process by
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:ref:`poisoning <poison_btb>` the branch target buffer. This can
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influence the indirect branch targets for a victim process that either
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runs later on the same hardware thread, or running concurrently on
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a sibling hardware thread sharing the same physical core.
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A user process can protect itself against Spectre variant 2 attacks
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by using the prctl() syscall to disable indirect branch speculation
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for itself. An administrator can also cordon off an unsafe process
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from polluting the branch target buffer by disabling the process's
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indirect branch speculation. This comes with a performance cost
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from not using indirect branch speculation and clearing the branch
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target buffer. When SMT is enabled on x86, for a process that has
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indirect branch speculation disabled, Single Threaded Indirect Branch
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Predictors (STIBP) :ref:`[4] <spec_ref4>` are turned on to prevent the
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sibling thread from controlling branch target buffer. In addition,
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the Indirect Branch Prediction Barrier (IBPB) is issued to clear the
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branch target buffer when context switching to and from such process.
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On x86, the return stack buffer is stuffed on context switch.
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This prevents the branch target buffer from being used for branch
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prediction when the return stack buffer underflows while switching to
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a deeper call stack. Any poisoned entries in the return stack buffer
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left by the previous process will also be cleared.
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User programs should use address space randomization to make attacks
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more difficult (Set /proc/sys/kernel/randomize_va_space = 1 or 2).
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3. A virtualized guest attacking the host
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The attack mechanism is similar to how user processes attack the
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kernel. The kernel is entered via hyper-calls or other virtualization
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exit paths.
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For Spectre variant 1 attacks, rogue guests can pass parameters
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(e.g. in registers) via hyper-calls to derive invalid pointers to
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speculate into privileged memory after entering the kernel. For places
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where such kernel code has been identified, nospec accessor macros
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are used to stop speculative memory access.
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For Spectre variant 2 attacks, rogue guests can :ref:`poison
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<poison_btb>` the branch target buffer or return stack buffer, causing
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the kernel to jump to gadget code in the speculative execution paths.
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To mitigate variant 2, the host kernel can use return trampolines
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for indirect branches to bypass the poisoned branch target buffer,
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and flushing the return stack buffer on VM exit. This prevents rogue
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guests from affecting indirect branching in the host kernel.
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To protect host processes from rogue guests, host processes can have
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indirect branch speculation disabled via prctl(). The branch target
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buffer is cleared before context switching to such processes.
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4. A virtualized guest attacking other guest
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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A rogue guest may attack another guest to get data accessible by the
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other guest.
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Spectre variant 1 attacks are possible if parameters can be passed
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between guests. This may be done via mechanisms such as shared memory
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or message passing. Such parameters could be used to derive data
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pointers to privileged data in guest. The privileged data could be
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accessed by gadget code in the victim's speculation paths.
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Spectre variant 2 attacks can be launched from a rogue guest by
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:ref:`poisoning <poison_btb>` the branch target buffer or the return
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stack buffer. Such poisoned entries could be used to influence
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speculation execution paths in the victim guest.
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Linux kernel mitigates attacks to other guests running in the same
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CPU hardware thread by flushing the return stack buffer on VM exit,
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and clearing the branch target buffer before switching to a new guest.
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If SMT is used, Spectre variant 2 attacks from an untrusted guest
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in the sibling hyperthread can be mitigated by the administrator,
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by turning off the unsafe guest's indirect branch speculation via
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prctl(). A guest can also protect itself by turning on microcode
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based mitigations (such as IBPB or STIBP on x86) within the guest.
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.. _spectre_sys_info:
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Spectre system information
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--------------------------
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The Linux kernel provides a sysfs interface to enumerate the current
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mitigation status of the system for Spectre: whether the system is
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vulnerable, and which mitigations are active.
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The sysfs file showing Spectre variant 1 mitigation status is:
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/sys/devices/system/cpu/vulnerabilities/spectre_v1
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The possible values in this file are:
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.. list-table::
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* - 'Not affected'
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- The processor is not vulnerable.
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* - 'Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers'
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- The swapgs protections are disabled; otherwise it has
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protection in the kernel on a case by case base with explicit
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pointer sanitation and usercopy LFENCE barriers.
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* - 'Mitigation: usercopy/swapgs barriers and __user pointer sanitization'
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- Protection in the kernel on a case by case base with explicit
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pointer sanitation, usercopy LFENCE barriers, and swapgs LFENCE
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barriers.
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However, the protections are put in place on a case by case basis,
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and there is no guarantee that all possible attack vectors for Spectre
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variant 1 are covered.
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The spectre_v2 kernel file reports if the kernel has been compiled with
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retpoline mitigation or if the CPU has hardware mitigation, and if the
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CPU has support for additional process-specific mitigation.
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This file also reports CPU features enabled by microcode to mitigate
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attack between user processes:
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1. Indirect Branch Prediction Barrier (IBPB) to add additional
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isolation between processes of different users.
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2. Single Thread Indirect Branch Predictors (STIBP) to add additional
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isolation between CPU threads running on the same core.
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These CPU features may impact performance when used and can be enabled
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per process on a case-by-case base.
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The sysfs file showing Spectre variant 2 mitigation status is:
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/sys/devices/system/cpu/vulnerabilities/spectre_v2
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The possible values in this file are:
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- Kernel status:
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======================================== =================================
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'Not affected' The processor is not vulnerable
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'Mitigation: None' Vulnerable, no mitigation
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'Mitigation: Retpolines' Use Retpoline thunks
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'Mitigation: LFENCE' Use LFENCE instructions
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'Mitigation: Enhanced IBRS' Hardware-focused mitigation
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'Mitigation: Enhanced IBRS + Retpolines' Hardware-focused + Retpolines
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'Mitigation: Enhanced IBRS + LFENCE' Hardware-focused + LFENCE
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======================================== =================================
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- Firmware status: Show if Indirect Branch Restricted Speculation (IBRS) is
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used to protect against Spectre variant 2 attacks when calling firmware (x86 only).
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========== =============================================================
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'IBRS_FW' Protection against user program attacks when calling firmware
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========== =============================================================
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- Indirect branch prediction barrier (IBPB) status for protection between
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processes of different users. This feature can be controlled through
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prctl() per process, or through kernel command line options. This is
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an x86 only feature. For more details see below.
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=================== ========================================================
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'IBPB: disabled' IBPB unused
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'IBPB: always-on' Use IBPB on all tasks
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'IBPB: conditional' Use IBPB on SECCOMP or indirect branch restricted tasks
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=================== ========================================================
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- Single threaded indirect branch prediction (STIBP) status for protection
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between different hyper threads. This feature can be controlled through
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prctl per process, or through kernel command line options. This is x86
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only feature. For more details see below.
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==================== ========================================================
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'STIBP: disabled' STIBP unused
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'STIBP: forced' Use STIBP on all tasks
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'STIBP: conditional' Use STIBP on SECCOMP or indirect branch restricted tasks
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==================== ========================================================
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- Return stack buffer (RSB) protection status:
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============= ===========================================
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'RSB filling' Protection of RSB on context switch enabled
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============= ===========================================
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- EIBRS Post-barrier Return Stack Buffer (PBRSB) protection status:
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=========================== =======================================================
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'PBRSB-eIBRS: SW sequence' CPU is affected and protection of RSB on VMEXIT enabled
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'PBRSB-eIBRS: Vulnerable' CPU is vulnerable
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'PBRSB-eIBRS: Not affected' CPU is not affected by PBRSB
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=========================== =======================================================
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- Branch History Injection (BHI) protection status:
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.. list-table::
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* - BHI: Not affected
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- System is not affected
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* - BHI: Retpoline
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- System is protected by retpoline
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* - BHI: BHI_DIS_S
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- System is protected by BHI_DIS_S
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* - BHI: SW loop, KVM SW loop
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- System is protected by software clearing sequence
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* - BHI: Vulnerable
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- System is vulnerable to BHI
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* - BHI: Vulnerable, KVM: SW loop
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- System is vulnerable; KVM is protected by software clearing sequence
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Full mitigation might require a microcode update from the CPU
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vendor. When the necessary microcode is not available, the kernel will
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report vulnerability.
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Turning on mitigation for Spectre variant 1 and Spectre variant 2
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-----------------------------------------------------------------
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1. Kernel mitigation
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^^^^^^^^^^^^^^^^^^^^
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Spectre variant 1
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~~~~~~~~~~~~~~~~~
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For the Spectre variant 1, vulnerable kernel code (as determined
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by code audit or scanning tools) is annotated on a case by case
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basis to use nospec accessor macros for bounds clipping :ref:`[2]
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<spec_ref2>` to avoid any usable disclosure gadgets. However, it may
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not cover all attack vectors for Spectre variant 1.
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Copy-from-user code has an LFENCE barrier to prevent the access_ok()
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check from being mis-speculated. The barrier is done by the
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barrier_nospec() macro.
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For the swapgs variant of Spectre variant 1, LFENCE barriers are
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added to interrupt, exception and NMI entry where needed. These
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barriers are done by the FENCE_SWAPGS_KERNEL_ENTRY and
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FENCE_SWAPGS_USER_ENTRY macros.
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Spectre variant 2
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~~~~~~~~~~~~~~~~~
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For Spectre variant 2 mitigation, the compiler turns indirect calls or
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jumps in the kernel into equivalent return trampolines (retpolines)
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:ref:`[3] <spec_ref3>` :ref:`[9] <spec_ref9>` to go to the target
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addresses. Speculative execution paths under retpolines are trapped
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in an infinite loop to prevent any speculative execution jumping to
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a gadget.
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To turn on retpoline mitigation on a vulnerable CPU, the kernel
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needs to be compiled with a gcc compiler that supports the
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-mindirect-branch=thunk-extern -mindirect-branch-register options.
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|
If the kernel is compiled with a Clang compiler, the compiler needs
|
|
to support -mretpoline-external-thunk option. The kernel config
|
|
CONFIG_MITIGATION_RETPOLINE needs to be turned on, and the CPU needs
|
|
to run with the latest updated microcode.
|
|
|
|
On Intel Skylake-era systems the mitigation covers most, but not all,
|
|
cases. See :ref:`[3] <spec_ref3>` for more details.
|
|
|
|
On CPUs with hardware mitigation for Spectre variant 2 (e.g. IBRS
|
|
or enhanced IBRS on x86), retpoline is automatically disabled at run time.
|
|
|
|
Systems which support enhanced IBRS (eIBRS) enable IBRS protection once at
|
|
boot, by setting the IBRS bit, and they're automatically protected against
|
|
some Spectre v2 variant attacks. The BHB can still influence the choice of
|
|
indirect branch predictor entry, and although branch predictor entries are
|
|
isolated between modes when eIBRS is enabled, the BHB itself is not isolated
|
|
between modes. Systems which support BHI_DIS_S will set it to protect against
|
|
BHI attacks.
|
|
|
|
On Intel's enhanced IBRS systems, this includes cross-thread branch target
|
|
injections on SMT systems (STIBP). In other words, Intel eIBRS enables
|
|
STIBP, too.
|
|
|
|
AMD Automatic IBRS does not protect userspace, and Legacy IBRS systems clear
|
|
the IBRS bit on exit to userspace, therefore both explicitly enable STIBP.
|
|
|
|
The retpoline mitigation is turned on by default on vulnerable
|
|
CPUs. It can be forced on or off by the administrator
|
|
via the kernel command line and sysfs control files. See
|
|
:ref:`spectre_mitigation_control_command_line`.
|
|
|
|
On x86, indirect branch restricted speculation is turned on by default
|
|
before invoking any firmware code to prevent Spectre variant 2 exploits
|
|
using the firmware.
|
|
|
|
Using kernel address space randomization (CONFIG_RANDOMIZE_SLAB=y
|
|
and CONFIG_SLAB_FREELIST_RANDOM=y in the kernel configuration) makes
|
|
attacks on the kernel generally more difficult.
|
|
|
|
2. User program mitigation
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
User programs can mitigate Spectre variant 1 using LFENCE or "bounds
|
|
clipping". For more details see :ref:`[2] <spec_ref2>`.
|
|
|
|
For Spectre variant 2 mitigation, individual user programs
|
|
can be compiled with return trampolines for indirect branches.
|
|
This protects them from consuming poisoned entries in the branch
|
|
target buffer left by malicious software.
|
|
|
|
On legacy IBRS systems, at return to userspace, implicit STIBP is disabled
|
|
because the kernel clears the IBRS bit. In this case, the userspace programs
|
|
can disable indirect branch speculation via prctl() (See
|
|
:ref:`Documentation/userspace-api/spec_ctrl.rst <set_spec_ctrl>`).
|
|
On x86, this will turn on STIBP to guard against attacks from the
|
|
sibling thread when the user program is running, and use IBPB to
|
|
flush the branch target buffer when switching to/from the program.
|
|
|
|
Restricting indirect branch speculation on a user program will
|
|
also prevent the program from launching a variant 2 attack
|
|
on x86. Administrators can change that behavior via the kernel
|
|
command line and sysfs control files.
|
|
See :ref:`spectre_mitigation_control_command_line`.
|
|
|
|
Programs that disable their indirect branch speculation will have
|
|
more overhead and run slower.
|
|
|
|
User programs should use address space randomization
|
|
(/proc/sys/kernel/randomize_va_space = 1 or 2) to make attacks more
|
|
difficult.
|
|
|
|
3. VM mitigation
|
|
^^^^^^^^^^^^^^^^
|
|
|
|
Within the kernel, Spectre variant 1 attacks from rogue guests are
|
|
mitigated on a case by case basis in VM exit paths. Vulnerable code
|
|
uses nospec accessor macros for "bounds clipping", to avoid any
|
|
usable disclosure gadgets. However, this may not cover all variant
|
|
1 attack vectors.
|
|
|
|
For Spectre variant 2 attacks from rogue guests to the kernel, the
|
|
Linux kernel uses retpoline or Enhanced IBRS to prevent consumption of
|
|
poisoned entries in branch target buffer left by rogue guests. It also
|
|
flushes the return stack buffer on every VM exit to prevent a return
|
|
stack buffer underflow so poisoned branch target buffer could be used,
|
|
or attacker guests leaving poisoned entries in the return stack buffer.
|
|
|
|
To mitigate guest-to-guest attacks in the same CPU hardware thread,
|
|
the branch target buffer is sanitized by flushing before switching
|
|
to a new guest on a CPU.
|
|
|
|
The above mitigations are turned on by default on vulnerable CPUs.
|
|
|
|
To mitigate guest-to-guest attacks from sibling thread when SMT is
|
|
in use, an untrusted guest running in the sibling thread can have
|
|
its indirect branch speculation disabled by administrator via prctl().
|
|
|
|
The kernel also allows guests to use any microcode based mitigation
|
|
they choose to use (such as IBPB or STIBP on x86) to protect themselves.
|
|
|
|
.. _spectre_mitigation_control_command_line:
|
|
|
|
Mitigation control on the kernel command line
|
|
---------------------------------------------
|
|
|
|
Spectre variant 2 mitigation can be disabled or force enabled at the
|
|
kernel command line.
|
|
|
|
nospectre_v1
|
|
|
|
[X86,PPC] Disable mitigations for Spectre Variant 1
|
|
(bounds check bypass). With this option data leaks are
|
|
possible in the system.
|
|
|
|
nospectre_v2
|
|
|
|
[X86] Disable all mitigations for the Spectre variant 2
|
|
(indirect branch prediction) vulnerability. System may
|
|
allow data leaks with this option, which is equivalent
|
|
to spectre_v2=off.
|
|
|
|
|
|
spectre_v2=
|
|
|
|
[X86] Control mitigation of Spectre variant 2
|
|
(indirect branch speculation) vulnerability.
|
|
The default operation protects the kernel from
|
|
user space attacks.
|
|
|
|
on
|
|
unconditionally enable, implies
|
|
spectre_v2_user=on
|
|
off
|
|
unconditionally disable, implies
|
|
spectre_v2_user=off
|
|
auto
|
|
kernel detects whether your CPU model is
|
|
vulnerable
|
|
|
|
Selecting 'on' will, and 'auto' may, choose a
|
|
mitigation method at run time according to the
|
|
CPU, the available microcode, the setting of the
|
|
CONFIG_MITIGATION_RETPOLINE configuration option,
|
|
and the compiler with which the kernel was built.
|
|
|
|
Selecting 'on' will also enable the mitigation
|
|
against user space to user space task attacks.
|
|
|
|
Selecting 'off' will disable both the kernel and
|
|
the user space protections.
|
|
|
|
Specific mitigations can also be selected manually:
|
|
|
|
retpoline auto pick between generic,lfence
|
|
retpoline,generic Retpolines
|
|
retpoline,lfence LFENCE; indirect branch
|
|
retpoline,amd alias for retpoline,lfence
|
|
eibrs Enhanced/Auto IBRS
|
|
eibrs,retpoline Enhanced/Auto IBRS + Retpolines
|
|
eibrs,lfence Enhanced/Auto IBRS + LFENCE
|
|
ibrs use IBRS to protect kernel
|
|
|
|
Not specifying this option is equivalent to
|
|
spectre_v2=auto.
|
|
|
|
In general the kernel by default selects
|
|
reasonable mitigations for the current CPU. To
|
|
disable Spectre variant 2 mitigations, boot with
|
|
spectre_v2=off. Spectre variant 1 mitigations
|
|
cannot be disabled.
|
|
|
|
spectre_bhi=
|
|
|
|
[X86] Control mitigation of Branch History Injection
|
|
(BHI) vulnerability. This setting affects the deployment
|
|
of the HW BHI control and the SW BHB clearing sequence.
|
|
|
|
on
|
|
(default) Enable the HW or SW mitigation as
|
|
needed.
|
|
off
|
|
Disable the mitigation.
|
|
|
|
For spectre_v2_user see Documentation/admin-guide/kernel-parameters.txt
|
|
|
|
Mitigation selection guide
|
|
--------------------------
|
|
|
|
1. Trusted userspace
|
|
^^^^^^^^^^^^^^^^^^^^
|
|
|
|
If all userspace applications are from trusted sources and do not
|
|
execute externally supplied untrusted code, then the mitigations can
|
|
be disabled.
|
|
|
|
2. Protect sensitive programs
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
For security-sensitive programs that have secrets (e.g. crypto
|
|
keys), protection against Spectre variant 2 can be put in place by
|
|
disabling indirect branch speculation when the program is running
|
|
(See :ref:`Documentation/userspace-api/spec_ctrl.rst <set_spec_ctrl>`).
|
|
|
|
3. Sandbox untrusted programs
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
Untrusted programs that could be a source of attacks can be cordoned
|
|
off by disabling their indirect branch speculation when they are run
|
|
(See :ref:`Documentation/userspace-api/spec_ctrl.rst <set_spec_ctrl>`).
|
|
This prevents untrusted programs from polluting the branch target
|
|
buffer. This behavior can be changed via the kernel command line
|
|
and sysfs control files. See
|
|
:ref:`spectre_mitigation_control_command_line`.
|
|
|
|
3. High security mode
|
|
^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
All Spectre variant 2 mitigations can be forced on
|
|
at boot time for all programs (See the "on" option in
|
|
:ref:`spectre_mitigation_control_command_line`). This will add
|
|
overhead as indirect branch speculations for all programs will be
|
|
restricted.
|
|
|
|
On x86, branch target buffer will be flushed with IBPB when switching
|
|
to a new program. STIBP is left on all the time to protect programs
|
|
against variant 2 attacks originating from programs running on
|
|
sibling threads.
|
|
|
|
Alternatively, STIBP can be used only when running programs
|
|
whose indirect branch speculation is explicitly disabled,
|
|
while IBPB is still used all the time when switching to a new
|
|
program to clear the branch target buffer (See "ibpb" option in
|
|
:ref:`spectre_mitigation_control_command_line`). This "ibpb" option
|
|
has less performance cost than the "on" option, which leaves STIBP
|
|
on all the time.
|
|
|
|
References on Spectre
|
|
---------------------
|
|
|
|
Intel white papers:
|
|
|
|
.. _spec_ref1:
|
|
|
|
[1] `Intel analysis of speculative execution side channels <https://newsroom.intel.com/wp-content/uploads/sites/11/2018/01/Intel-Analysis-of-Speculative-Execution-Side-Channels.pdf>`_.
|
|
|
|
.. _spec_ref2:
|
|
|
|
[2] `Bounds check bypass <https://software.intel.com/security-software-guidance/software-guidance/bounds-check-bypass>`_.
|
|
|
|
.. _spec_ref3:
|
|
|
|
[3] `Deep dive: Retpoline: A branch target injection mitigation <https://software.intel.com/security-software-guidance/insights/deep-dive-retpoline-branch-target-injection-mitigation>`_.
|
|
|
|
.. _spec_ref4:
|
|
|
|
[4] `Deep Dive: Single Thread Indirect Branch Predictors <https://software.intel.com/security-software-guidance/insights/deep-dive-single-thread-indirect-branch-predictors>`_.
|
|
|
|
AMD white papers:
|
|
|
|
.. _spec_ref5:
|
|
|
|
[5] `AMD64 technology indirect branch control extension <https://developer.amd.com/wp-content/resources/Architecture_Guidelines_Update_Indirect_Branch_Control.pdf>`_.
|
|
|
|
.. _spec_ref6:
|
|
|
|
[6] `Software techniques for managing speculation on AMD processors <https://developer.amd.com/wp-content/resources/Managing-Speculation-on-AMD-Processors.pdf>`_.
|
|
|
|
ARM white papers:
|
|
|
|
.. _spec_ref7:
|
|
|
|
[7] `Cache speculation side-channels <https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/download-the-whitepaper>`_.
|
|
|
|
.. _spec_ref8:
|
|
|
|
[8] `Cache speculation issues update <https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/latest-updates/cache-speculation-issues-update>`_.
|
|
|
|
Google white paper:
|
|
|
|
.. _spec_ref9:
|
|
|
|
[9] `Retpoline: a software construct for preventing branch-target-injection <https://support.google.com/faqs/answer/7625886>`_.
|
|
|
|
MIPS white paper:
|
|
|
|
.. _spec_ref10:
|
|
|
|
[10] `MIPS: response on speculative execution and side channel vulnerabilities <https://www.mips.com/blog/mips-response-on-speculative-execution-and-side-channel-vulnerabilities/>`_.
|
|
|
|
Academic papers:
|
|
|
|
.. _spec_ref11:
|
|
|
|
[11] `Spectre Attacks: Exploiting Speculative Execution <https://spectreattack.com/spectre.pdf>`_.
|
|
|
|
.. _spec_ref12:
|
|
|
|
[12] `NetSpectre: Read Arbitrary Memory over Network <https://arxiv.org/abs/1807.10535>`_.
|
|
|
|
.. _spec_ref13:
|
|
|
|
[13] `Spectre Returns! Speculation Attacks using the Return Stack Buffer <https://www.usenix.org/system/files/conference/woot18/woot18-paper-koruyeh.pdf>`_.
|