261 lines
12 KiB
ReStructuredText
261 lines
12 KiB
ReStructuredText
=========================================
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Processor MMIO Stale Data Vulnerabilities
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=========================================
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Processor MMIO Stale Data Vulnerabilities are a class of memory-mapped I/O
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(MMIO) vulnerabilities that can expose data. The sequences of operations for
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exposing data range from simple to very complex. Because most of the
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vulnerabilities require the attacker to have access to MMIO, many environments
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are not affected. System environments using virtualization where MMIO access is
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provided to untrusted guests may need mitigation. These vulnerabilities are
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not transient execution attacks. However, these vulnerabilities may propagate
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stale data into core fill buffers where the data can subsequently be inferred
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by an unmitigated transient execution attack. Mitigation for these
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vulnerabilities includes a combination of microcode update and software
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changes, depending on the platform and usage model. Some of these mitigations
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are similar to those used to mitigate Microarchitectural Data Sampling (MDS) or
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those used to mitigate Special Register Buffer Data Sampling (SRBDS).
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Data Propagators
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================
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Propagators are operations that result in stale data being copied or moved from
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one microarchitectural buffer or register to another. Processor MMIO Stale Data
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Vulnerabilities are operations that may result in stale data being directly
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read into an architectural, software-visible state or sampled from a buffer or
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register.
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Fill Buffer Stale Data Propagator (FBSDP)
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-----------------------------------------
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Stale data may propagate from fill buffers (FB) into the non-coherent portion
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of the uncore on some non-coherent writes. Fill buffer propagation by itself
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does not make stale data architecturally visible. Stale data must be propagated
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to a location where it is subject to reading or sampling.
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Sideband Stale Data Propagator (SSDP)
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-------------------------------------
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The sideband stale data propagator (SSDP) is limited to the client (including
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Intel Xeon server E3) uncore implementation. The sideband response buffer is
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shared by all client cores. For non-coherent reads that go to sideband
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destinations, the uncore logic returns 64 bytes of data to the core, including
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both requested data and unrequested stale data, from a transaction buffer and
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the sideband response buffer. As a result, stale data from the sideband
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response and transaction buffers may now reside in a core fill buffer.
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Primary Stale Data Propagator (PSDP)
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------------------------------------
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The primary stale data propagator (PSDP) is limited to the client (including
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Intel Xeon server E3) uncore implementation. Similar to the sideband response
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buffer, the primary response buffer is shared by all client cores. For some
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processors, MMIO primary reads will return 64 bytes of data to the core fill
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buffer including both requested data and unrequested stale data. This is
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similar to the sideband stale data propagator.
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Vulnerabilities
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===============
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Device Register Partial Write (DRPW) (CVE-2022-21166)
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-----------------------------------------------------
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Some endpoint MMIO registers incorrectly handle writes that are smaller than
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the register size. Instead of aborting the write or only copying the correct
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subset of bytes (for example, 2 bytes for a 2-byte write), more bytes than
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specified by the write transaction may be written to the register. On
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processors affected by FBSDP, this may expose stale data from the fill buffers
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of the core that created the write transaction.
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Shared Buffers Data Sampling (SBDS) (CVE-2022-21125)
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----------------------------------------------------
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After propagators may have moved data around the uncore and copied stale data
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into client core fill buffers, processors affected by MFBDS can leak data from
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the fill buffer. It is limited to the client (including Intel Xeon server E3)
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uncore implementation.
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Shared Buffers Data Read (SBDR) (CVE-2022-21123)
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------------------------------------------------
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It is similar to Shared Buffer Data Sampling (SBDS) except that the data is
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directly read into the architectural software-visible state. It is limited to
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the client (including Intel Xeon server E3) uncore implementation.
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Affected Processors
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===================
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Not all the CPUs are affected by all the variants. For instance, most
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processors for the server market (excluding Intel Xeon E3 processors) are
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impacted by only Device Register Partial Write (DRPW).
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Below is the list of affected Intel processors [#f1]_:
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=================== ============ =========
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Common name Family_Model Steppings
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=================== ============ =========
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HASWELL_X 06_3FH 2,4
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SKYLAKE_L 06_4EH 3
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BROADWELL_X 06_4FH All
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SKYLAKE_X 06_55H 3,4,6,7,11
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BROADWELL_D 06_56H 3,4,5
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SKYLAKE 06_5EH 3
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ICELAKE_X 06_6AH 4,5,6
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ICELAKE_D 06_6CH 1
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ICELAKE_L 06_7EH 5
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ATOM_TREMONT_D 06_86H All
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LAKEFIELD 06_8AH 1
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KABYLAKE_L 06_8EH 9 to 12
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ATOM_TREMONT 06_96H 1
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ATOM_TREMONT_L 06_9CH 0
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KABYLAKE 06_9EH 9 to 13
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COMETLAKE 06_A5H 2,3,5
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COMETLAKE_L 06_A6H 0,1
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ROCKETLAKE 06_A7H 1
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=================== ============ =========
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If a CPU is in the affected processor list, but not affected by a variant, it
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is indicated by new bits in MSR IA32_ARCH_CAPABILITIES. As described in a later
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section, mitigation largely remains the same for all the variants, i.e. to
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clear the CPU fill buffers via VERW instruction.
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New bits in MSRs
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================
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Newer processors and microcode update on existing affected processors added new
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bits to IA32_ARCH_CAPABILITIES MSR. These bits can be used to enumerate
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specific variants of Processor MMIO Stale Data vulnerabilities and mitigation
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capability.
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MSR IA32_ARCH_CAPABILITIES
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--------------------------
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Bit 13 - SBDR_SSDP_NO - When set, processor is not affected by either the
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Shared Buffers Data Read (SBDR) vulnerability or the sideband stale
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data propagator (SSDP).
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Bit 14 - FBSDP_NO - When set, processor is not affected by the Fill Buffer
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Stale Data Propagator (FBSDP).
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Bit 15 - PSDP_NO - When set, processor is not affected by Primary Stale Data
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Propagator (PSDP).
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Bit 17 - FB_CLEAR - When set, VERW instruction will overwrite CPU fill buffer
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values as part of MD_CLEAR operations. Processors that do not
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enumerate MDS_NO (meaning they are affected by MDS) but that do
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enumerate support for both L1D_FLUSH and MD_CLEAR implicitly enumerate
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FB_CLEAR as part of their MD_CLEAR support.
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Bit 18 - FB_CLEAR_CTRL - Processor supports read and write to MSR
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IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]. On such processors, the FB_CLEAR_DIS
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bit can be set to cause the VERW instruction to not perform the
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FB_CLEAR action. Not all processors that support FB_CLEAR will support
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FB_CLEAR_CTRL.
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MSR IA32_MCU_OPT_CTRL
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---------------------
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Bit 3 - FB_CLEAR_DIS - When set, VERW instruction does not perform the FB_CLEAR
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action. This may be useful to reduce the performance impact of FB_CLEAR in
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cases where system software deems it warranted (for example, when performance
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is more critical, or the untrusted software has no MMIO access). Note that
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FB_CLEAR_DIS has no impact on enumeration (for example, it does not change
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FB_CLEAR or MD_CLEAR enumeration) and it may not be supported on all processors
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that enumerate FB_CLEAR.
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Mitigation
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==========
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Like MDS, all variants of Processor MMIO Stale Data vulnerabilities have the
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same mitigation strategy to force the CPU to clear the affected buffers before
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an attacker can extract the secrets.
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This is achieved by using the otherwise unused and obsolete VERW instruction in
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combination with a microcode update. The microcode clears the affected CPU
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buffers when the VERW instruction is executed.
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Kernel reuses the MDS function to invoke the buffer clearing:
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mds_clear_cpu_buffers()
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On MDS affected CPUs, the kernel already invokes CPU buffer clear on
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kernel/userspace, hypervisor/guest and C-state (idle) transitions. No
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additional mitigation is needed on such CPUs.
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For CPUs not affected by MDS or TAA, mitigation is needed only for the attacker
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with MMIO capability. Therefore, VERW is not required for kernel/userspace. For
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virtualization case, VERW is only needed at VMENTER for a guest with MMIO
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capability.
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Mitigation points
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-----------------
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Return to user space
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^^^^^^^^^^^^^^^^^^^^
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Same mitigation as MDS when affected by MDS/TAA, otherwise no mitigation
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needed.
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C-State transition
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^^^^^^^^^^^^^^^^^^
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Control register writes by CPU during C-state transition can propagate data
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from fill buffer to uncore buffers. Execute VERW before C-state transition to
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clear CPU fill buffers.
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Guest entry point
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^^^^^^^^^^^^^^^^^
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Same mitigation as MDS when processor is also affected by MDS/TAA, otherwise
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execute VERW at VMENTER only for MMIO capable guests. On CPUs not affected by
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MDS/TAA, guest without MMIO access cannot extract secrets using Processor MMIO
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Stale Data vulnerabilities, so there is no need to execute VERW for such guests.
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Mitigation control on the kernel command line
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---------------------------------------------
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The kernel command line allows to control the Processor MMIO Stale Data
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mitigations at boot time with the option "mmio_stale_data=". The valid
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arguments for this option are:
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========== =================================================================
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full If the CPU is vulnerable, enable mitigation; CPU buffer clearing
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on exit to userspace and when entering a VM. Idle transitions are
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protected as well. It does not automatically disable SMT.
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full,nosmt Same as full, with SMT disabled on vulnerable CPUs. This is the
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complete mitigation.
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off Disables mitigation completely.
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========== =================================================================
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If the CPU is affected and mmio_stale_data=off is not supplied on the kernel
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command line, then the kernel selects the appropriate mitigation.
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Mitigation status information
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-----------------------------
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The Linux kernel provides a sysfs interface to enumerate the current
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vulnerability status of the system: whether the system is vulnerable, and
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which mitigations are active. The relevant sysfs file is:
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/sys/devices/system/cpu/vulnerabilities/mmio_stale_data
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The possible values in this file are:
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.. list-table::
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* - 'Not affected'
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- The processor is not vulnerable
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* - 'Vulnerable'
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- The processor is vulnerable, but no mitigation enabled
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* - 'Vulnerable: Clear CPU buffers attempted, no microcode'
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- The processor is vulnerable, but microcode is not updated. The
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mitigation is enabled on a best effort basis.
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* - 'Mitigation: Clear CPU buffers'
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- The processor is vulnerable and the CPU buffer clearing mitigation is
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enabled.
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* - 'Unknown: No mitigations'
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- The processor vulnerability status is unknown because it is
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out of Servicing period. Mitigation is not attempted.
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Definitions:
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------------
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Servicing period: The process of providing functional and security updates to
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Intel processors or platforms, utilizing the Intel Platform Update (IPU)
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process or other similar mechanisms.
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End of Servicing Updates (ESU): ESU is the date at which Intel will no
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longer provide Servicing, such as through IPU or other similar update
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processes. ESU dates will typically be aligned to end of quarter.
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If the processor is vulnerable then the following information is appended to
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the above information:
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======================== ===========================================
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'SMT vulnerable' SMT is enabled
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'SMT disabled' SMT is disabled
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'SMT Host state unknown' Kernel runs in a VM, Host SMT state unknown
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======================== ===========================================
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References
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----------
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.. [#f1] Affected Processors
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https://www.intel.com/content/www/us/en/developer/topic-technology/software-security-guidance/processors-affected-consolidated-product-cpu-model.html
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