312 lines
11 KiB
ReStructuredText
312 lines
11 KiB
ReStructuredText
MDS - Microarchitectural Data Sampling
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======================================
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Microarchitectural Data Sampling is a hardware vulnerability which allows
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unprivileged speculative access to data which is available in various CPU
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internal buffers.
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Affected processors
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-------------------
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This vulnerability affects a wide range of Intel processors. The
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vulnerability is not present on:
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- Processors from AMD, Centaur and other non Intel vendors
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- Older processor models, where the CPU family is < 6
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- Some Atoms (Bonnell, Saltwell, Goldmont, GoldmontPlus)
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- Intel processors which have the ARCH_CAP_MDS_NO bit set in the
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IA32_ARCH_CAPABILITIES MSR.
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Whether a processor is affected or not can be read out from the MDS
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vulnerability file in sysfs. See :ref:`mds_sys_info`.
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Not all processors are affected by all variants of MDS, but the mitigation
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is identical for all of them so the kernel treats them as a single
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vulnerability.
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Related CVEs
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------------
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The following CVE entries are related to the MDS vulnerability:
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============== ===== ===================================================
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CVE-2018-12126 MSBDS Microarchitectural Store Buffer Data Sampling
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CVE-2018-12130 MFBDS Microarchitectural Fill Buffer Data Sampling
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CVE-2018-12127 MLPDS Microarchitectural Load Port Data Sampling
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CVE-2019-11091 MDSUM Microarchitectural Data Sampling Uncacheable Memory
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============== ===== ===================================================
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Problem
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-------
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When performing store, load, L1 refill operations, processors write data
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into temporary microarchitectural structures (buffers). The data in the
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buffer can be forwarded to load operations as an optimization.
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Under certain conditions, usually a fault/assist caused by a load
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operation, data unrelated to the load memory address can be speculatively
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forwarded from the buffers. Because the load operation causes a fault or
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assist and its result will be discarded, the forwarded data will not cause
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incorrect program execution or state changes. But a malicious operation
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may be able to forward this speculative data to a disclosure gadget which
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allows in turn to infer the value via a cache side channel attack.
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Because the buffers are potentially shared between Hyper-Threads cross
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Hyper-Thread attacks are possible.
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Deeper technical information is available in the MDS specific x86
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architecture section: :ref:`Documentation/x86/mds.rst <mds>`.
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Attack scenarios
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----------------
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Attacks against the MDS vulnerabilities can be mounted from malicious non-
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privileged user space applications running on hosts or guest. Malicious
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guest OSes can obviously mount attacks as well.
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Contrary to other speculation based vulnerabilities the MDS vulnerability
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does not allow the attacker to control the memory target address. As a
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consequence the attacks are purely sampling based, but as demonstrated with
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the TLBleed attack samples can be postprocessed successfully.
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Web-Browsers
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^^^^^^^^^^^^
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It's unclear whether attacks through Web-Browsers are possible at
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all. The exploitation through Java-Script is considered very unlikely,
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but other widely used web technologies like Webassembly could possibly be
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abused.
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.. _mds_sys_info:
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MDS system information
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-----------------------
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The Linux kernel provides a sysfs interface to enumerate the current MDS
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status of the system: whether the system is vulnerable, and which
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mitigations are active. The relevant sysfs file is:
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/sys/devices/system/cpu/vulnerabilities/mds
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The possible values in this file are:
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.. list-table::
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* - 'Not affected'
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- The processor is not vulnerable
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* - 'Vulnerable'
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- The processor is vulnerable, but no mitigation enabled
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* - 'Vulnerable: Clear CPU buffers attempted, no microcode'
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- The processor is vulnerable but microcode is not updated.
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The mitigation is enabled on a best effort basis. See :ref:`vmwerv`
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* - 'Mitigation: Clear CPU buffers'
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- The processor is vulnerable and the CPU buffer clearing mitigation is
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enabled.
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If the processor is vulnerable then the following information is appended
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to the above information:
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======================== ============================================
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'SMT vulnerable' SMT is enabled
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'SMT mitigated' SMT is enabled and mitigated
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'SMT disabled' SMT is disabled
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'SMT Host state unknown' Kernel runs in a VM, Host SMT state unknown
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======================== ============================================
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.. _vmwerv:
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Best effort mitigation mode
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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If the processor is vulnerable, but the availability of the microcode based
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mitigation mechanism is not advertised via CPUID the kernel selects a best
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effort mitigation mode. This mode invokes the mitigation instructions
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without a guarantee that they clear the CPU buffers.
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This is done to address virtualization scenarios where the host has the
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microcode update applied, but the hypervisor is not yet updated to expose
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the CPUID to the guest. If the host has updated microcode the protection
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takes effect otherwise a few cpu cycles are wasted pointlessly.
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The state in the mds sysfs file reflects this situation accordingly.
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Mitigation mechanism
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-------------------------
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The kernel detects the affected CPUs and the presence of the microcode
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which is required.
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If a CPU is affected and the microcode is available, then the kernel
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enables the mitigation by default. The mitigation can be controlled at boot
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time via a kernel command line option. See
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:ref:`mds_mitigation_control_command_line`.
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.. _cpu_buffer_clear:
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CPU buffer clearing
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^^^^^^^^^^^^^^^^^^^
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The mitigation for MDS clears the affected CPU buffers on return to user
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space and when entering a guest.
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If SMT is enabled it also clears the buffers on idle entry when the CPU
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is only affected by MSBDS and not any other MDS variant, because the
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other variants cannot be protected against cross Hyper-Thread attacks.
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For CPUs which are only affected by MSBDS the user space, guest and idle
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transition mitigations are sufficient and SMT is not affected.
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.. _virt_mechanism:
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Virtualization mitigation
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^^^^^^^^^^^^^^^^^^^^^^^^^
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The protection for host to guest transition depends on the L1TF
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vulnerability of the CPU:
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- CPU is affected by L1TF:
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If the L1D flush mitigation is enabled and up to date microcode is
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available, the L1D flush mitigation is automatically protecting the
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guest transition.
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If the L1D flush mitigation is disabled then the MDS mitigation is
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invoked explicit when the host MDS mitigation is enabled.
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For details on L1TF and virtualization see:
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:ref:`Documentation/admin-guide/hw-vuln//l1tf.rst <mitigation_control_kvm>`.
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- CPU is not affected by L1TF:
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CPU buffers are flushed before entering the guest when the host MDS
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mitigation is enabled.
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The resulting MDS protection matrix for the host to guest transition:
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============ ===== ============= ============ =================
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L1TF MDS VMX-L1FLUSH Host MDS MDS-State
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Don't care No Don't care N/A Not affected
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Yes Yes Disabled Off Vulnerable
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Yes Yes Disabled Full Mitigated
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Yes Yes Enabled Don't care Mitigated
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No Yes N/A Off Vulnerable
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No Yes N/A Full Mitigated
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============ ===== ============= ============ =================
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This only covers the host to guest transition, i.e. prevents leakage from
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host to guest, but does not protect the guest internally. Guests need to
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have their own protections.
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.. _xeon_phi:
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XEON PHI specific considerations
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The XEON PHI processor family is affected by MSBDS which can be exploited
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cross Hyper-Threads when entering idle states. Some XEON PHI variants allow
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to use MWAIT in user space (Ring 3) which opens an potential attack vector
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for malicious user space. The exposure can be disabled on the kernel
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command line with the 'ring3mwait=disable' command line option.
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XEON PHI is not affected by the other MDS variants and MSBDS is mitigated
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before the CPU enters a idle state. As XEON PHI is not affected by L1TF
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either disabling SMT is not required for full protection.
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.. _mds_smt_control:
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SMT control
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^^^^^^^^^^^
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All MDS variants except MSBDS can be attacked cross Hyper-Threads. That
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means on CPUs which are affected by MFBDS or MLPDS it is necessary to
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disable SMT for full protection. These are most of the affected CPUs; the
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exception is XEON PHI, see :ref:`xeon_phi`.
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Disabling SMT can have a significant performance impact, but the impact
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depends on the type of workloads.
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See the relevant chapter in the L1TF mitigation documentation for details:
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:ref:`Documentation/admin-guide/hw-vuln/l1tf.rst <smt_control>`.
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.. _mds_mitigation_control_command_line:
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Mitigation control on the kernel command line
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---------------------------------------------
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The kernel command line allows to control the MDS mitigations at boot
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time with the option "mds=". The valid arguments for this option are:
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============ =============================================================
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full If the CPU is vulnerable, enable all available mitigations
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for the MDS vulnerability, CPU buffer clearing on exit to
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userspace and when entering a VM. Idle transitions are
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protected as well if SMT is enabled.
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It does not automatically disable SMT.
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full,nosmt The same as mds=full, with SMT disabled on vulnerable
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CPUs. This is the complete mitigation.
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off Disables MDS mitigations completely.
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============ =============================================================
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Not specifying this option is equivalent to "mds=full". For processors
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that are affected by both TAA (TSX Asynchronous Abort) and MDS,
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specifying just "mds=off" without an accompanying "tsx_async_abort=off"
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will have no effect as the same mitigation is used for both
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vulnerabilities.
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Mitigation selection guide
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--------------------------
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1. Trusted userspace
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^^^^^^^^^^^^^^^^^^^^
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If all userspace applications are from a trusted source and do not
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execute untrusted code which is supplied externally, then the mitigation
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can be disabled.
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2. Virtualization with trusted guests
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The same considerations as above versus trusted user space apply.
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3. Virtualization with untrusted guests
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The protection depends on the state of the L1TF mitigations.
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See :ref:`virt_mechanism`.
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If the MDS mitigation is enabled and SMT is disabled, guest to host and
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guest to guest attacks are prevented.
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.. _mds_default_mitigations:
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Default mitigations
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-------------------
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The kernel default mitigations for vulnerable processors are:
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- Enable CPU buffer clearing
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The kernel does not by default enforce the disabling of SMT, which leaves
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SMT systems vulnerable when running untrusted code. The same rationale as
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for L1TF applies.
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See :ref:`Documentation/admin-guide/hw-vuln//l1tf.rst <default_mitigations>`.
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