99 lines
3.6 KiB
Plaintext
99 lines
3.6 KiB
Plaintext
TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
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OMAP CONTROL PHY
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Required properties:
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- compatible: Should be one of
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"ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
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"ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
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e.g. USB2_PHY on OMAP5.
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"ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
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e.g. USB3 PHY and SATA PHY on OMAP5.
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"ti,control-phy-pcie" - for pcie to support external clock for pcie and to
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set PCS delay value.
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e.g. PCIE PHY in DRA7x
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"ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
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DRA7 platform.
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"ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
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AM437 platform.
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- reg : register ranges as listed in the reg-names property
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- reg-names: "otghs_control" for control-phy-otghs
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"power", "pcie_pcs" and "control_sma" for control-phy-pcie
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"power" for all other types
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omap_control_usb: omap-control-usb@4a002300 {
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compatible = "ti,control-phy-otghs";
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reg = <0x4a00233c 0x4>;
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reg-names = "otghs_control";
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};
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TI PIPE3 PHY
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Required properties:
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- compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or
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"ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated.
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- reg : Address and length of the register set for the device.
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- reg-names: The names of the register addresses corresponding to the registers
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filled in "reg".
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- #phy-cells: determine the number of cells that should be given in the
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phandle while referencing this phy.
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- clocks: a list of phandles and clock-specifier pairs, one for each entry in
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clock-names.
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- clock-names: should include:
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* "wkupclk" - wakeup clock.
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* "sysclk" - system clock.
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* "refclk" - reference clock.
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* "dpll_ref" - external dpll ref clk
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* "dpll_ref_m2" - external dpll ref clk
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* "phy-div" - divider for apll
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* "div-clk" - apll clock
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Optional properties:
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- id: If there are multiple instance of the same type, in order to
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differentiate between each instance "id" can be used (e.g., multi-lane PCIe
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PHY). If "id" is not provided, it is set to default value of '1'.
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- syscon-pllreset: Handle to system control region that contains the
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CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
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register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
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- syscon-pcs : phandle/offset pair. Phandle to the system control module and the
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register offset to write the PCS delay value.
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Deprecated properties:
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- ctrl-module : phandle of the control module used by PHY driver to power on
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the PHY.
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Recommended properties:
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- syscon-phy-power : phandle/offset pair. Phandle to the system control
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module and the register offset to power on/off the PHY.
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This is usually a subnode of ocp2scp to which it is connected.
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usb3phy@4a084400 {
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compatible = "ti,phy-usb3";
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reg = <0x4a084400 0x80>,
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<0x4a084800 0x64>,
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<0x4a084c00 0x40>;
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reg-names = "phy_rx", "phy_tx", "pll_ctrl";
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ctrl-module = <&omap_control_usb>;
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#phy-cells = <0>;
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clocks = <&usb_phy_cm_clk32k>,
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<&sys_clkin>,
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<&usb_otg_ss_refclk960m>;
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clock-names = "wkupclk",
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"sysclk",
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"refclk";
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};
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sata_phy: phy@4a096000 {
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compatible = "ti,phy-pipe3-sata";
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reg = <0x4A096000 0x80>, /* phy_rx */
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<0x4A096400 0x64>, /* phy_tx */
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<0x4A096800 0x40>; /* pll_ctrl */
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reg-names = "phy_rx", "phy_tx", "pll_ctrl";
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ctrl-module = <&omap_control_sata>;
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clocks = <&sys_clkin1>, <&sata_ref_clk>;
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clock-names = "sysclk", "refclk";
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syscon-pllreset = <&scm_conf 0x3fc>;
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#phy-cells = <0>;
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};
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