423 lines
12 KiB
C
423 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Cadence MHDP8546 DP bridge driver.
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*
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* Copyright (C) 2020 Cadence Design Systems, Inc.
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*
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* Author: Quentin Schulz <quentin.schulz@free-electrons.com>
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* Swapnil Jakhade <sjakhade@cadence.com>
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*/
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#ifndef CDNS_MHDP8546_CORE_H
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#define CDNS_MHDP8546_CORE_H
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#include <linux/bits.h>
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#include <linux/mutex.h>
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#include <linux/spinlock.h>
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#include <drm/display/drm_dp_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_connector.h>
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struct clk;
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struct device;
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struct phy;
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/* Register offsets */
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#define CDNS_APB_CTRL 0x00000
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#define CDNS_CPU_STALL BIT(3)
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#define CDNS_MAILBOX_FULL 0x00008
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#define CDNS_MAILBOX_EMPTY 0x0000c
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#define CDNS_MAILBOX_TX_DATA 0x00010
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#define CDNS_MAILBOX_RX_DATA 0x00014
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#define CDNS_KEEP_ALIVE 0x00018
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#define CDNS_KEEP_ALIVE_MASK GENMASK(7, 0)
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#define CDNS_VER_L 0x0001C
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#define CDNS_VER_H 0x00020
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#define CDNS_LIB_L_ADDR 0x00024
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#define CDNS_LIB_H_ADDR 0x00028
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#define CDNS_MB_INT_MASK 0x00034
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#define CDNS_MB_INT_STATUS 0x00038
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#define CDNS_SW_CLK_L 0x0003c
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#define CDNS_SW_CLK_H 0x00040
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#define CDNS_SW_EVENT0 0x00044
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#define CDNS_DPTX_HPD BIT(0)
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#define CDNS_HDCP_TX_STATUS BIT(4)
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#define CDNS_HDCP2_TX_IS_KM_STORED BIT(5)
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#define CDNS_HDCP2_TX_STORE_KM BIT(6)
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#define CDNS_HDCP_TX_IS_RCVR_ID_VALID BIT(7)
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#define CDNS_SW_EVENT1 0x00048
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#define CDNS_SW_EVENT2 0x0004c
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#define CDNS_SW_EVENT3 0x00050
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#define CDNS_APB_INT_MASK 0x0006C
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#define CDNS_APB_INT_MASK_MAILBOX_INT BIT(0)
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#define CDNS_APB_INT_MASK_SW_EVENT_INT BIT(1)
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#define CDNS_APB_INT_STATUS 0x00070
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#define CDNS_DPTX_CAR 0x00904
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#define CDNS_VIF_CLK_EN BIT(0)
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#define CDNS_VIF_CLK_RSTN BIT(1)
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#define CDNS_SOURCE_VIDEO_IF(s) (0x00b00 + ((s) * 0x20))
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#define CDNS_BND_HSYNC2VSYNC(s) (CDNS_SOURCE_VIDEO_IF(s) + \
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0x00)
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#define CDNS_IP_DTCT_WIN GENMASK(11, 0)
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#define CDNS_IP_DET_INTERLACE_FORMAT BIT(12)
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#define CDNS_IP_BYPASS_V_INTERFACE BIT(13)
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#define CDNS_HSYNC2VSYNC_POL_CTRL(s) (CDNS_SOURCE_VIDEO_IF(s) + \
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0x10)
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#define CDNS_H2V_HSYNC_POL_ACTIVE_LOW BIT(1)
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#define CDNS_H2V_VSYNC_POL_ACTIVE_LOW BIT(2)
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#define CDNS_DPTX_PHY_CONFIG 0x02000
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#define CDNS_PHY_TRAINING_EN BIT(0)
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#define CDNS_PHY_TRAINING_TYPE(x) (((x) & GENMASK(3, 0)) << 1)
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#define CDNS_PHY_SCRAMBLER_BYPASS BIT(5)
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#define CDNS_PHY_ENCODER_BYPASS BIT(6)
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#define CDNS_PHY_SKEW_BYPASS BIT(7)
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#define CDNS_PHY_TRAINING_AUTO BIT(8)
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#define CDNS_PHY_LANE0_SKEW(x) (((x) & GENMASK(2, 0)) << 9)
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#define CDNS_PHY_LANE1_SKEW(x) (((x) & GENMASK(2, 0)) << 12)
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#define CDNS_PHY_LANE2_SKEW(x) (((x) & GENMASK(2, 0)) << 15)
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#define CDNS_PHY_LANE3_SKEW(x) (((x) & GENMASK(2, 0)) << 18)
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#define CDNS_PHY_COMMON_CONFIG (CDNS_PHY_LANE1_SKEW(1) | \
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CDNS_PHY_LANE2_SKEW(2) | \
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CDNS_PHY_LANE3_SKEW(3))
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#define CDNS_PHY_10BIT_EN BIT(21)
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#define CDNS_DP_FRAMER_GLOBAL_CONFIG 0x02200
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#define CDNS_DP_NUM_LANES(x) ((x) - 1)
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#define CDNS_DP_MST_EN BIT(2)
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#define CDNS_DP_FRAMER_EN BIT(3)
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#define CDNS_DP_RATE_GOVERNOR_EN BIT(4)
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#define CDNS_DP_NO_VIDEO_MODE BIT(5)
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#define CDNS_DP_DISABLE_PHY_RST BIT(6)
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#define CDNS_DP_WR_FAILING_EDGE_VSYNC BIT(7)
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#define CDNS_DP_FRAMER_TU 0x02208
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#define CDNS_DP_FRAMER_TU_SIZE(x) (((x) & GENMASK(6, 0)) << 8)
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#define CDNS_DP_FRAMER_TU_VS(x) ((x) & GENMASK(5, 0))
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#define CDNS_DP_FRAMER_TU_CNT_RST_EN BIT(15)
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#define CDNS_DP_MTPH_CONTROL 0x02264
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#define CDNS_DP_MTPH_ECF_EN BIT(0)
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#define CDNS_DP_MTPH_ACT_EN BIT(1)
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#define CDNS_DP_MTPH_LVP_EN BIT(2)
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#define CDNS_DP_MTPH_STATUS 0x0226C
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#define CDNS_DP_MTPH_ACT_STATUS BIT(0)
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#define CDNS_DP_LANE_EN 0x02300
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#define CDNS_DP_LANE_EN_LANES(x) GENMASK((x) - 1, 0)
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#define CDNS_DP_ENHNCD 0x02304
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#define CDNS_DPTX_STREAM(s) (0x03000 + (s) * 0x80)
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#define CDNS_DP_MSA_HORIZONTAL_0(s) (CDNS_DPTX_STREAM(s) + 0x00)
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#define CDNS_DP_MSAH0_H_TOTAL(x) (x)
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#define CDNS_DP_MSAH0_HSYNC_START(x) ((x) << 16)
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#define CDNS_DP_MSA_HORIZONTAL_1(s) (CDNS_DPTX_STREAM(s) + 0x04)
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#define CDNS_DP_MSAH1_HSYNC_WIDTH(x) (x)
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#define CDNS_DP_MSAH1_HSYNC_POL_LOW BIT(15)
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#define CDNS_DP_MSAH1_HDISP_WIDTH(x) ((x) << 16)
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#define CDNS_DP_MSA_VERTICAL_0(s) (CDNS_DPTX_STREAM(s) + 0x08)
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#define CDNS_DP_MSAV0_V_TOTAL(x) (x)
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#define CDNS_DP_MSAV0_VSYNC_START(x) ((x) << 16)
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#define CDNS_DP_MSA_VERTICAL_1(s) (CDNS_DPTX_STREAM(s) + 0x0c)
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#define CDNS_DP_MSAV1_VSYNC_WIDTH(x) (x)
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#define CDNS_DP_MSAV1_VSYNC_POL_LOW BIT(15)
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#define CDNS_DP_MSAV1_VDISP_WIDTH(x) ((x) << 16)
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#define CDNS_DP_MSA_MISC(s) (CDNS_DPTX_STREAM(s) + 0x10)
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#define CDNS_DP_STREAM_CONFIG(s) (CDNS_DPTX_STREAM(s) + 0x14)
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#define CDNS_DP_STREAM_CONFIG_2(s) (CDNS_DPTX_STREAM(s) + 0x2c)
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#define CDNS_DP_SC2_TU_VS_DIFF(x) ((x) << 8)
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#define CDNS_DP_HORIZONTAL(s) (CDNS_DPTX_STREAM(s) + 0x30)
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#define CDNS_DP_H_HSYNC_WIDTH(x) (x)
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#define CDNS_DP_H_H_TOTAL(x) ((x) << 16)
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#define CDNS_DP_VERTICAL_0(s) (CDNS_DPTX_STREAM(s) + 0x34)
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#define CDNS_DP_V0_VHEIGHT(x) (x)
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#define CDNS_DP_V0_VSTART(x) ((x) << 16)
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#define CDNS_DP_VERTICAL_1(s) (CDNS_DPTX_STREAM(s) + 0x38)
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#define CDNS_DP_V1_VTOTAL(x) (x)
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#define CDNS_DP_V1_VTOTAL_EVEN BIT(16)
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#define CDNS_DP_MST_SLOT_ALLOCATE(s) (CDNS_DPTX_STREAM(s) + 0x44)
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#define CDNS_DP_S_ALLOC_START_SLOT(x) (x)
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#define CDNS_DP_S_ALLOC_END_SLOT(x) ((x) << 8)
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#define CDNS_DP_RATE_GOVERNING(s) (CDNS_DPTX_STREAM(s) + 0x48)
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#define CDNS_DP_RG_TARG_AV_SLOTS_Y(x) (x)
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#define CDNS_DP_RG_TARG_AV_SLOTS_X(x) ((x) << 4)
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#define CDNS_DP_RG_ENABLE BIT(10)
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#define CDNS_DP_FRAMER_PXL_REPR(s) (CDNS_DPTX_STREAM(s) + 0x4c)
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#define CDNS_DP_FRAMER_6_BPC BIT(0)
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#define CDNS_DP_FRAMER_8_BPC BIT(1)
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#define CDNS_DP_FRAMER_10_BPC BIT(2)
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#define CDNS_DP_FRAMER_12_BPC BIT(3)
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#define CDNS_DP_FRAMER_16_BPC BIT(4)
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#define CDNS_DP_FRAMER_PXL_FORMAT 0x8
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#define CDNS_DP_FRAMER_RGB BIT(0)
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#define CDNS_DP_FRAMER_YCBCR444 BIT(1)
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#define CDNS_DP_FRAMER_YCBCR422 BIT(2)
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#define CDNS_DP_FRAMER_YCBCR420 BIT(3)
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#define CDNS_DP_FRAMER_Y_ONLY BIT(4)
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#define CDNS_DP_FRAMER_SP(s) (CDNS_DPTX_STREAM(s) + 0x50)
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#define CDNS_DP_FRAMER_VSYNC_POL_LOW BIT(0)
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#define CDNS_DP_FRAMER_HSYNC_POL_LOW BIT(1)
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#define CDNS_DP_FRAMER_INTERLACE BIT(2)
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#define CDNS_DP_LINE_THRESH(s) (CDNS_DPTX_STREAM(s) + 0x64)
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#define CDNS_DP_ACTIVE_LINE_THRESH(x) (x)
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#define CDNS_DP_VB_ID(s) (CDNS_DPTX_STREAM(s) + 0x68)
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#define CDNS_DP_VB_ID_INTERLACED BIT(2)
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#define CDNS_DP_VB_ID_COMPRESSED BIT(6)
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#define CDNS_DP_FRONT_BACK_PORCH(s) (CDNS_DPTX_STREAM(s) + 0x78)
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#define CDNS_DP_BACK_PORCH(x) (x)
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#define CDNS_DP_FRONT_PORCH(x) ((x) << 16)
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#define CDNS_DP_BYTE_COUNT(s) (CDNS_DPTX_STREAM(s) + 0x7c)
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#define CDNS_DP_BYTE_COUNT_BYTES_IN_CHUNK_SHIFT 16
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/* mailbox */
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#define MAILBOX_RETRY_US 1000
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#define MAILBOX_TIMEOUT_US 2000000
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#define MB_OPCODE_ID 0
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#define MB_MODULE_ID 1
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#define MB_SIZE_MSB_ID 2
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#define MB_SIZE_LSB_ID 3
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#define MB_DATA_ID 4
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#define MB_MODULE_ID_DP_TX 0x01
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#define MB_MODULE_ID_HDCP_TX 0x07
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#define MB_MODULE_ID_HDCP_RX 0x08
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#define MB_MODULE_ID_HDCP_GENERAL 0x09
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#define MB_MODULE_ID_GENERAL 0x0a
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/* firmware and opcodes */
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#define FW_NAME "cadence/mhdp8546.bin"
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#define CDNS_MHDP_IMEM 0x10000
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#define GENERAL_MAIN_CONTROL 0x01
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#define GENERAL_TEST_ECHO 0x02
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#define GENERAL_BUS_SETTINGS 0x03
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#define GENERAL_TEST_ACCESS 0x04
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#define GENERAL_REGISTER_READ 0x07
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#define DPTX_SET_POWER_MNG 0x00
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#define DPTX_GET_EDID 0x02
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#define DPTX_READ_DPCD 0x03
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#define DPTX_WRITE_DPCD 0x04
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#define DPTX_ENABLE_EVENT 0x05
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#define DPTX_WRITE_REGISTER 0x06
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#define DPTX_READ_REGISTER 0x07
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#define DPTX_WRITE_FIELD 0x08
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#define DPTX_READ_EVENT 0x0a
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#define DPTX_GET_LAST_AUX_STAUS 0x0e
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#define DPTX_HPD_STATE 0x11
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#define DPTX_ADJUST_LT 0x12
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#define FW_STANDBY 0
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#define FW_ACTIVE 1
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/* HPD */
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#define DPTX_READ_EVENT_HPD_TO_HIGH BIT(0)
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#define DPTX_READ_EVENT_HPD_TO_LOW BIT(1)
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#define DPTX_READ_EVENT_HPD_PULSE BIT(2)
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#define DPTX_READ_EVENT_HPD_STATE BIT(3)
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/* general */
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#define CDNS_DP_TRAINING_PATTERN_4 0x7
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#define CDNS_KEEP_ALIVE_TIMEOUT 2000
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#define CDNS_VOLT_SWING(x) ((x) & GENMASK(1, 0))
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#define CDNS_FORCE_VOLT_SWING BIT(2)
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#define CDNS_PRE_EMPHASIS(x) ((x) & GENMASK(1, 0))
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#define CDNS_FORCE_PRE_EMPHASIS BIT(2)
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#define CDNS_SUPPORT_TPS(x) BIT((x) - 1)
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#define CDNS_FAST_LINK_TRAINING BIT(0)
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#define CDNS_LANE_MAPPING_TYPE_C_LANE_0(x) ((x) & GENMASK(1, 0))
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#define CDNS_LANE_MAPPING_TYPE_C_LANE_1(x) ((x) & GENMASK(3, 2))
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#define CDNS_LANE_MAPPING_TYPE_C_LANE_2(x) ((x) & GENMASK(5, 4))
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#define CDNS_LANE_MAPPING_TYPE_C_LANE_3(x) ((x) & GENMASK(7, 6))
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#define CDNS_LANE_MAPPING_NORMAL 0xe4
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#define CDNS_LANE_MAPPING_FLIPPED 0x1b
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#define CDNS_DP_MAX_NUM_LANES 4
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#define CDNS_DP_TEST_VSC_SDP BIT(6) /* 1.3+ */
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#define CDNS_DP_TEST_COLOR_FORMAT_RAW_Y_ONLY BIT(7)
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#define CDNS_MHDP_MAX_STREAMS 4
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#define DP_LINK_CAP_ENHANCED_FRAMING BIT(0)
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struct cdns_mhdp_link {
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unsigned char revision;
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unsigned int rate;
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unsigned int num_lanes;
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unsigned long capabilities;
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};
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struct cdns_mhdp_host {
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unsigned int link_rate;
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u8 lanes_cnt;
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u8 volt_swing;
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u8 pre_emphasis;
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u8 pattern_supp;
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u8 lane_mapping;
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bool fast_link;
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bool enhanced;
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bool scrambler;
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bool ssc;
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};
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struct cdns_mhdp_sink {
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unsigned int link_rate;
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u8 lanes_cnt;
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u8 pattern_supp;
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bool fast_link;
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bool enhanced;
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bool ssc;
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};
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struct cdns_mhdp_display_fmt {
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u32 color_format;
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u32 bpc;
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bool y_only;
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};
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/*
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* These enums present MHDP hw initialization state
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* Legal state transitions are:
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* MHDP_HW_READY <-> MHDP_HW_STOPPED
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*/
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enum mhdp_hw_state {
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MHDP_HW_READY = 1, /* HW ready, FW active */
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MHDP_HW_STOPPED /* Driver removal FW to be stopped */
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};
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struct cdns_mhdp_device;
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struct mhdp_platform_ops {
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int (*init)(struct cdns_mhdp_device *mhdp);
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void (*exit)(struct cdns_mhdp_device *mhdp);
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void (*enable)(struct cdns_mhdp_device *mhdp);
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void (*disable)(struct cdns_mhdp_device *mhdp);
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};
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struct cdns_mhdp_bridge_state {
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struct drm_bridge_state base;
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struct drm_display_mode *current_mode;
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};
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struct cdns_mhdp_platform_info {
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const struct drm_bridge_timings *timings;
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const struct mhdp_platform_ops *ops;
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};
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#define to_cdns_mhdp_bridge_state(s) \
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container_of(s, struct cdns_mhdp_bridge_state, base)
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struct cdns_mhdp_hdcp {
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struct delayed_work check_work;
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struct work_struct prop_work;
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struct mutex mutex; /* mutex to protect hdcp.value */
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u32 value;
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u8 hdcp_content_type;
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};
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struct cdns_mhdp_device {
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void __iomem *regs;
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void __iomem *sapb_regs;
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void __iomem *j721e_regs;
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struct device *dev;
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struct clk *clk;
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struct phy *phy;
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const struct cdns_mhdp_platform_info *info;
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/* This is to protect mailbox communications with the firmware */
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struct mutex mbox_mutex;
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/*
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* "link_mutex" protects the access to all the link parameters
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* including the link training process. Link training will be
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* invoked both from threaded interrupt handler and from atomic
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* callbacks when link_up is not set. So this mutex protects
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* flags such as link_up, bridge_enabled, link.num_lanes,
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* link.rate etc.
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*/
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struct mutex link_mutex;
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struct drm_connector connector;
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struct drm_bridge bridge;
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struct cdns_mhdp_link link;
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struct drm_dp_aux aux;
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struct cdns_mhdp_host host;
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struct cdns_mhdp_sink sink;
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struct cdns_mhdp_display_fmt display_fmt;
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u8 stream_id;
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bool link_up;
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bool plugged;
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/*
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* "start_lock" protects the access to bridge_attached and
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* hw_state data members that control the delayed firmware
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* loading and attaching the bridge. They are accessed from
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* both the DRM core and cdns_mhdp_fw_cb(). In most cases just
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* protecting the data members is enough, but the irq mask
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* setting needs to be protected when enabling the FW.
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*/
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spinlock_t start_lock;
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bool bridge_attached;
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bool bridge_enabled;
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enum mhdp_hw_state hw_state;
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wait_queue_head_t fw_load_wq;
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/* Work struct to schedule a uevent on link train failure */
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struct work_struct modeset_retry_work;
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struct work_struct hpd_work;
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wait_queue_head_t sw_events_wq;
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u32 sw_events;
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struct cdns_mhdp_hdcp hdcp;
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bool hdcp_supported;
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};
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#define connector_to_mhdp(x) container_of(x, struct cdns_mhdp_device, connector)
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#define bridge_to_mhdp(x) container_of(x, struct cdns_mhdp_device, bridge)
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u32 cdns_mhdp_wait_for_sw_event(struct cdns_mhdp_device *mhdp, uint32_t event);
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#endif
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