71 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			71 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| /*
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|  * Copyright 2016 Linaro Ltd
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|  *
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|  * Permission is hereby granted, free of charge, to any person obtaining a copy
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|  * of this software and associated documentation files (the "Software"), to deal
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|  * in the Software without restriction, including without limitation the rights
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|  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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|  * copies of the Software, and to permit persons to whom the Software is
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|  * furnished to do so, subject to the following conditions:
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|  *
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|  * The above copyright notice and this permission notice shall be included in
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|  * all copies or substantial portions of the Software.
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|  *
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|  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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|  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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|  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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|  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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|  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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|  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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|  * THE SOFTWARE.
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|  */
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| 
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| /dts-v1/;
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| #include "arm-realview-eb-mp.dtsi"
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| 
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| / {
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| 	model = "ARM RealView EB Cortex A9 MPCore";
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| 
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| 	/*
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| 	 * This is the Cortex A9 MPCore tile used with the
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| 	 * RealView EB.
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| 	 */
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| 	cpus {
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| 		#address-cells = <1>;
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| 		#size-cells = <0>;
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| 		enable-method = "arm,realview-smp";
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| 
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| 		A9_0: cpu@0 {
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| 			device_type = "cpu";
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| 			compatible = "arm,cortex-a9";
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| 			reg = <0>;
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| 			next-level-cache = <&L2>;
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| 		};
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| 
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| 		A9_1: cpu@1 {
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| 			device_type = "cpu";
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| 			compatible = "arm,cortex-a9";
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| 			reg = <1>;
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| 			next-level-cache = <&L2>;
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| 		};
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| 
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| 		A9_2: cpu@2 {
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| 			device_type = "cpu";
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| 			compatible = "arm,cortex-a9";
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| 			reg = <2>;
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| 			next-level-cache = <&L2>;
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| 		};
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| 
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| 		A9_3: cpu@3 {
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| 			device_type = "cpu";
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| 			compatible = "arm,cortex-a9";
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| 			reg = <3>;
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| 			next-level-cache = <&L2>;
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| 		};
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| 	};
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| };
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| 
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| &pmu {
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| 	interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
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| };
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