651 lines
18 KiB
C
651 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Hardware interface of the NX-GZIP compression accelerator
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*
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* Copyright (C) IBM Corporation, 2020
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*
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* Author: Bulent Abali <abali@us.ibm.com>
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*
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*/
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#ifndef _NXU_H
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#define _NXU_H
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#include <stdint.h>
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#include <endian.h>
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#include "nx.h"
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/* deflate */
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#define LLSZ 286
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#define DSZ 30
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/* nx */
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#define DHTSZ 18
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#define DHT_MAXSZ 288
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#define MAX_DDE_COUNT 256
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/* util */
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#ifdef NXDBG
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#define NXPRT(X) X
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#else
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#define NXPRT(X)
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#endif
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#ifdef NXTIMER
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#include <sys/platform/ppc.h>
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#define NX_CLK(X) X
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#define nx_get_time() __ppc_get_timebase()
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#define nx_get_freq() __ppc_get_timebase_freq()
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#else
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#define NX_CLK(X)
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#define nx_get_time() (-1)
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#define nx_get_freq() (-1)
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#endif
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#define NX_MAX_FAULTS 500
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/*
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* Definitions of acronyms used here. See
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* P9 NX Gzip Accelerator User's Manual for details:
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* https://github.com/libnxz/power-gzip/blob/develop/doc/power_nx_gzip_um.pdf
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*
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* adler/crc: 32 bit checksums appended to stream tail
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* ce: completion extension
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* cpb: coprocessor parameter block (metadata)
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* crb: coprocessor request block (command)
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* csb: coprocessor status block (status)
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* dht: dynamic huffman table
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* dde: data descriptor element (address, length)
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* ddl: list of ddes
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* dh/fh: dynamic and fixed huffman types
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* fc: coprocessor function code
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* histlen: history/dictionary length
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* history: sliding window of up to 32KB of data
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* lzcount: Deflate LZ symbol counts
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* rembytecnt: remaining byte count
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* sfbt: source final block type; last block's type during decomp
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* spbc: source processed byte count
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* subc: source unprocessed bit count
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* tebc: target ending bit count; valid bits in the last byte
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* tpbc: target processed byte count
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* vas: virtual accelerator switch; the user mode interface
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*/
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union nx_qw_t {
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uint32_t word[4];
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uint64_t dword[2];
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} __aligned(16);
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/*
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* Note: NX registers with fewer than 32 bits are declared by
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* convention as uint32_t variables in unions. If *_offset and *_mask
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* are defined for a variable, then use get_ put_ macros to
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* conveniently access the register fields for endian conversions.
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*/
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struct nx_dde_t {
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/* Data Descriptor Element, Section 6.4 */
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union {
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uint32_t dde_count;
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/* When dde_count == 0 ddead is a pointer to a data buffer;
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* ddebc is the buffer length bytes.
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* When dde_count > 0 dde is an indirect dde; ddead is a
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* pointer to a contiguous list of direct ddes; ddebc is the
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* total length of all data pointed to by the list of direct
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* ddes. Note that only one level of indirection is permitted.
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* See Section 6.4 of the user manual for additional details.
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*/
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};
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uint32_t ddebc; /* dde byte count */
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uint64_t ddead; /* dde address */
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} __aligned(16);
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struct nx_csb_t {
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/* Coprocessor Status Block, Section 6.6 */
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union {
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uint32_t csb_v;
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/* Valid bit. v must be set to 0 by the program
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* before submitting the coprocessor command.
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* Software can poll for the v bit
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*/
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uint32_t csb_f;
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/* 16B CSB size. Written to 0 by DMA when it writes the CPB */
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uint32_t csb_cs;
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/* cs completion sequence; unused */
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uint32_t csb_cc;
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/* cc completion code; cc != 0 exception occurred */
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uint32_t csb_ce;
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/* ce completion extension */
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};
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uint32_t tpbc;
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/* target processed byte count TPBC */
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uint64_t fsaddr;
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/* Section 6.12.1 CSB NonZero error summary. FSA Failing storage
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* address. Address where error occurred. When available, written
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* to A field of CSB
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*/
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} __aligned(16);
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struct nx_ccb_t {
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/* Coprocessor Completion Block, Section 6.7 */
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uint32_t reserved[3];
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union {
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/* When crb.c==0 (no ccb defined) it is reserved;
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* When crb.c==1 (ccb defined) it is cm
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*/
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uint32_t ccb_cm;
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/* Signal interrupt of crb.c==1 and cm==1 */
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uint32_t word;
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/* generic access to the 32bit word */
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};
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} __aligned(16);
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struct vas_stamped_crb_t {
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/*
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* CRB operand of the paste coprocessor instruction is stamped
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* in quadword 4 with the information shown here as its written
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* in to the receive FIFO of the coprocessor
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*/
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union {
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uint32_t vas_buf_num;
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/* Verification only vas buffer number which correlates to
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* the low order bits of the atag in the paste command
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*/
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uint32_t send_wc_id;
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/* Pointer to Send Window Context that provides for NX address
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* translation information, such as MSR and LPCR bits, job
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* completion interrupt RA, PSWID, and job utilization counter.
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*/
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};
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union {
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uint32_t recv_wc_id;
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/* Pointer to Receive Window Context. NX uses this to return
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* credits to a Receive FIFO as entries are dequeued.
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*/
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};
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uint32_t reserved2;
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union {
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uint32_t vas_invalid;
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/* Invalid bit. If this bit is 1 the CRB is discarded by
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* NX upon fetching from the receive FIFO. If this bit is 0
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* the CRB is processed normally. The bit is stamped to 0
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* by VAS and may be written to 1 by hypervisor while
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* the CRB is in the receive FIFO (in memory).
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*/
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};
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};
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struct nx_stamped_fault_crb_t {
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/*
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* A CRB that has a translation fault is stamped by NX in quadword 4
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* and pasted to the Fault Send Window in VAS.
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*/
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uint64_t fsa;
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union {
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uint32_t nxsf_t;
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uint32_t nxsf_fs;
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};
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uint32_t pswid;
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};
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union stamped_crb_t {
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struct vas_stamped_crb_t vas;
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struct nx_stamped_fault_crb_t nx;
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};
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struct nx_gzip_cpb_t {
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/*
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* Coprocessor Parameter Block In/Out are used to pass metadata
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* to/from accelerator. Tables 6.5 and 6.6 of the user manual.
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*/
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/* CPBInput */
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struct {
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union {
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union nx_qw_t qw0;
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struct {
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uint32_t in_adler; /* bits 0:31 */
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uint32_t in_crc; /* bits 32:63 */
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union {
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uint32_t in_histlen; /* bits 64:75 */
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uint32_t in_subc; /* bits 93:95 */
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};
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union {
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/* bits 108:111 */
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uint32_t in_sfbt;
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/* bits 112:127 */
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uint32_t in_rembytecnt;
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/* bits 116:127 */
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uint32_t in_dhtlen;
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};
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};
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};
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union {
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union nx_qw_t in_dht[DHTSZ]; /* qw[1:18] */
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char in_dht_char[DHT_MAXSZ]; /* byte access */
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};
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union nx_qw_t reserved[5]; /* qw[19:23] */
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};
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/* CPBOutput */
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volatile struct {
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union {
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union nx_qw_t qw24;
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struct {
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uint32_t out_adler; /* bits 0:31 qw[24] */
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uint32_t out_crc; /* bits 32:63 qw[24] */
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union {
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/* bits 77:79 qw[24] */
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uint32_t out_tebc;
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/* bits 80:95 qw[24] */
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uint32_t out_subc;
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};
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union {
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/* bits 108:111 qw[24] */
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uint32_t out_sfbt;
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/* bits 112:127 qw[24] */
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uint32_t out_rembytecnt;
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/* bits 116:127 qw[24] */
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uint32_t out_dhtlen;
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};
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};
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};
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union {
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union nx_qw_t qw25[79]; /* qw[25:103] */
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/* qw[25] compress no lzcounts or wrap */
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uint32_t out_spbc_comp_wrap;
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uint32_t out_spbc_wrap; /* qw[25] wrap */
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/* qw[25] compress no lzcounts */
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uint32_t out_spbc_comp;
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/* 286 LL and 30 D symbol counts */
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uint32_t out_lzcount[LLSZ+DSZ];
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struct {
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union nx_qw_t out_dht[DHTSZ]; /* qw[25:42] */
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/* qw[43] decompress */
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uint32_t out_spbc_decomp;
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};
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};
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/* qw[104] compress with lzcounts */
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uint32_t out_spbc_comp_with_count;
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};
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} __aligned(128);
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struct nx_gzip_crb_t {
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union { /* byte[0:3] */
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uint32_t gzip_fc; /* bits[24-31] */
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};
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uint32_t reserved1; /* byte[4:7] */
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union {
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uint64_t csb_address; /* byte[8:15] */
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struct {
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uint32_t reserved2;
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union {
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uint32_t crb_c;
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/* c==0 no ccb defined */
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uint32_t crb_at;
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/* at==0 address type is ignored;
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* all addrs effective assumed.
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*/
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};
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};
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};
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struct nx_dde_t source_dde; /* byte[16:31] */
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struct nx_dde_t target_dde; /* byte[32:47] */
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volatile struct nx_ccb_t ccb; /* byte[48:63] */
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volatile union {
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/* byte[64:239] shift csb by 128 bytes out of the crb; csb was
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* in crb earlier; JReilly says csb written with partial inject
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*/
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union nx_qw_t reserved64[11];
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union stamped_crb_t stamp; /* byte[64:79] */
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};
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volatile struct nx_csb_t csb;
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} __aligned(128);
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struct nx_gzip_crb_cpb_t {
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struct nx_gzip_crb_t crb;
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struct nx_gzip_cpb_t cpb;
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} __aligned(2048);
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/*
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* NX hardware convention has the msb bit on the left numbered 0.
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* The defines below has *_offset defined as the right most bit
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* position of a field. x of size_mask(x) is the field width in bits.
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*/
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#define size_mask(x) ((1U<<(x))-1)
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/*
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* Offsets and Widths within the containing 32 bits of the various NX
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* gzip hardware registers. Use the getnn/putnn macros to access
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* these regs
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*/
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#define dde_count_mask size_mask(8)
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#define dde_count_offset 23
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/* CSB */
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#define csb_v_mask size_mask(1)
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#define csb_v_offset 0
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#define csb_f_mask size_mask(1)
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#define csb_f_offset 6
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#define csb_cs_mask size_mask(8)
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#define csb_cs_offset 15
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#define csb_cc_mask size_mask(8)
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#define csb_cc_offset 23
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#define csb_ce_mask size_mask(8)
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#define csb_ce_offset 31
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/* CCB */
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#define ccb_cm_mask size_mask(3)
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#define ccb_cm_offset 31
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/* VAS stamped CRB fields */
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#define vas_buf_num_mask size_mask(6)
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#define vas_buf_num_offset 5
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#define send_wc_id_mask size_mask(16)
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#define send_wc_id_offset 31
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#define recv_wc_id_mask size_mask(16)
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#define recv_wc_id_offset 31
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#define vas_invalid_mask size_mask(1)
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#define vas_invalid_offset 31
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/* NX stamped fault CRB fields */
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#define nxsf_t_mask size_mask(1)
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#define nxsf_t_offset 23
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#define nxsf_fs_mask size_mask(8)
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#define nxsf_fs_offset 31
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/* CPB input */
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#define in_histlen_mask size_mask(12)
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#define in_histlen_offset 11
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#define in_dhtlen_mask size_mask(12)
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#define in_dhtlen_offset 31
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#define in_subc_mask size_mask(3)
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#define in_subc_offset 31
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#define in_sfbt_mask size_mask(4)
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#define in_sfbt_offset 15
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#define in_rembytecnt_mask size_mask(16)
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#define in_rembytecnt_offset 31
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/* CPB output */
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#define out_tebc_mask size_mask(3)
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#define out_tebc_offset 15
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#define out_subc_mask size_mask(16)
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#define out_subc_offset 31
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#define out_sfbt_mask size_mask(4)
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#define out_sfbt_offset 15
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#define out_rembytecnt_mask size_mask(16)
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#define out_rembytecnt_offset 31
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#define out_dhtlen_mask size_mask(12)
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#define out_dhtlen_offset 31
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/* CRB */
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#define gzip_fc_mask size_mask(8)
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#define gzip_fc_offset 31
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#define crb_c_mask size_mask(1)
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#define crb_c_offset 28
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#define crb_at_mask size_mask(1)
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#define crb_at_offset 30
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#define csb_address_mask ~(15UL) /* mask off bottom 4b */
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/*
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* Access macros for the registers. Do not access registers directly
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* because of the endian conversion. P9 processor may run either as
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* Little or Big endian. However the NX coprocessor regs are always
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* big endian.
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* Use the 32 and 64b macros to access respective
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* register sizes.
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* Use nn forms for the register fields shorter than 32 bits.
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*/
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#define getnn(ST, REG) ((be32toh(ST.REG) >> (31-REG##_offset)) \
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& REG##_mask)
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#define getpnn(ST, REG) ((be32toh((ST)->REG) >> (31-REG##_offset)) \
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& REG##_mask)
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#define get32(ST, REG) (be32toh(ST.REG))
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#define getp32(ST, REG) (be32toh((ST)->REG))
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#define get64(ST, REG) (be64toh(ST.REG))
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#define getp64(ST, REG) (be64toh((ST)->REG))
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#define unget32(ST, REG) (get32(ST, REG) & ~((REG##_mask) \
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<< (31-REG##_offset)))
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/* get 32bits less the REG field */
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#define ungetp32(ST, REG) (getp32(ST, REG) & ~((REG##_mask) \
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<< (31-REG##_offset)))
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/* get 32bits less the REG field */
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#define clear_regs(ST) memset((void *)(&(ST)), 0, sizeof(ST))
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#define clear_dde(ST) do { ST.dde_count = ST.ddebc = 0; ST.ddead = 0; \
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} while (0)
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#define clearp_dde(ST) do { (ST)->dde_count = (ST)->ddebc = 0; \
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(ST)->ddead = 0; \
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} while (0)
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#define clear_struct(ST) memset((void *)(&(ST)), 0, sizeof(ST))
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#define putnn(ST, REG, X) (ST.REG = htobe32(unget32(ST, REG) | (((X) \
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& REG##_mask) << (31-REG##_offset))))
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#define putpnn(ST, REG, X) ((ST)->REG = htobe32(ungetp32(ST, REG) \
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| (((X) & REG##_mask) << (31-REG##_offset))))
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#define put32(ST, REG, X) (ST.REG = htobe32(X))
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#define putp32(ST, REG, X) ((ST)->REG = htobe32(X))
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#define put64(ST, REG, X) (ST.REG = htobe64(X))
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#define putp64(ST, REG, X) ((ST)->REG = htobe64(X))
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/*
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* Completion extension ce(0) ce(1) ce(2). Bits ce(3-7)
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* unused. Section 6.6 Figure 6.7.
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*/
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#define get_csb_ce(ST) ((uint32_t)getnn(ST, csb_ce))
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#define get_csb_ce_ms3b(ST) (get_csb_ce(ST) >> 5)
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#define put_csb_ce_ms3b(ST, X) putnn(ST, csb_ce, ((uint32_t)(X) << 5))
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#define CSB_CE_PARTIAL 0x4
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#define CSB_CE_TERMINATE 0x2
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#define CSB_CE_TPBC_VALID 0x1
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#define csb_ce_termination(X) (!!((X) & CSB_CE_TERMINATE))
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/* termination, output buffers may be modified, SPBC/TPBC invalid Fig.6-7 */
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#define csb_ce_check_completion(X) (!csb_ce_termination(X))
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/* if not terminated then check full or partial completion */
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#define csb_ce_partial_completion(X) (!!((X) & CSB_CE_PARTIAL))
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#define csb_ce_full_completion(X) (!csb_ce_partial_completion(X))
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#define csb_ce_tpbc_valid(X) (!!((X) & CSB_CE_TPBC_VALID))
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/* TPBC indicates successfully stored data count */
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#define csb_ce_default_err(X) csb_ce_termination(X)
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/* most error CEs have CE(0)=0 and CE(1)=1 */
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#define csb_ce_cc3_partial(X) csb_ce_partial_completion(X)
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/* some CC=3 are partially completed, Table 6-8 */
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#define csb_ce_cc64(X) ((X)&(CSB_CE_PARTIAL \
|
|
| CSB_CE_TERMINATE) == 0)
|
|
/* Compression: when TPBC>SPBC then CC=64 Table 6-8; target didn't
|
|
* compress smaller than source.
|
|
*/
|
|
|
|
/* Decompress SFBT combinations Tables 5-3, 6-4, 6-6 */
|
|
|
|
#define SFBT_BFINAL 0x1
|
|
#define SFBT_LIT 0x4
|
|
#define SFBT_FHT 0x5
|
|
#define SFBT_DHT 0x6
|
|
#define SFBT_HDR 0x7
|
|
|
|
/*
|
|
* NX gzip function codes. Table 6.2.
|
|
* Bits 0:4 are the FC. Bit 5 is used by the DMA controller to
|
|
* select one of the two Byte Count Limits.
|
|
*/
|
|
|
|
#define GZIP_FC_LIMIT_MASK 0x01
|
|
#define GZIP_FC_COMPRESS_FHT 0x00
|
|
#define GZIP_FC_COMPRESS_DHT 0x02
|
|
#define GZIP_FC_COMPRESS_FHT_COUNT 0x04
|
|
#define GZIP_FC_COMPRESS_DHT_COUNT 0x06
|
|
#define GZIP_FC_COMPRESS_RESUME_FHT 0x08
|
|
#define GZIP_FC_COMPRESS_RESUME_DHT 0x0a
|
|
#define GZIP_FC_COMPRESS_RESUME_FHT_COUNT 0x0c
|
|
#define GZIP_FC_COMPRESS_RESUME_DHT_COUNT 0x0e
|
|
#define GZIP_FC_DECOMPRESS 0x10
|
|
#define GZIP_FC_DECOMPRESS_SINGLE_BLK_N_SUSPEND 0x12
|
|
#define GZIP_FC_DECOMPRESS_RESUME 0x14
|
|
#define GZIP_FC_DECOMPRESS_RESUME_SINGLE_BLK_N_SUSPEND 0x16
|
|
#define GZIP_FC_WRAP 0x1e
|
|
|
|
#define fc_is_compress(fc) (((fc) & 0x10) == 0)
|
|
#define fc_has_count(fc) (fc_is_compress(fc) && (((fc) & 0x4) != 0))
|
|
|
|
/* CSB.CC Error codes */
|
|
|
|
#define ERR_NX_OK 0
|
|
#define ERR_NX_ALIGNMENT 1
|
|
#define ERR_NX_OPOVERLAP 2
|
|
#define ERR_NX_DATA_LENGTH 3
|
|
#define ERR_NX_TRANSLATION 5
|
|
#define ERR_NX_PROTECTION 6
|
|
#define ERR_NX_EXTERNAL_UE7 7
|
|
#define ERR_NX_INVALID_OP 8
|
|
#define ERR_NX_PRIVILEGE 9
|
|
#define ERR_NX_INTERNAL_UE 10
|
|
#define ERR_NX_EXTERN_UE_WR 12
|
|
#define ERR_NX_TARGET_SPACE 13
|
|
#define ERR_NX_EXCESSIVE_DDE 14
|
|
#define ERR_NX_TRANSL_WR 15
|
|
#define ERR_NX_PROTECT_WR 16
|
|
#define ERR_NX_SUBFUNCTION 17
|
|
#define ERR_NX_FUNC_ABORT 18
|
|
#define ERR_NX_BYTE_MAX 19
|
|
#define ERR_NX_CORRUPT_CRB 20
|
|
#define ERR_NX_INVALID_CRB 21
|
|
#define ERR_NX_INVALID_DDE 30
|
|
#define ERR_NX_SEGMENTED_DDL 31
|
|
#define ERR_NX_DDE_OVERFLOW 33
|
|
#define ERR_NX_TPBC_GT_SPBC 64
|
|
#define ERR_NX_MISSING_CODE 66
|
|
#define ERR_NX_INVALID_DIST 67
|
|
#define ERR_NX_INVALID_DHT 68
|
|
#define ERR_NX_EXTERNAL_UE90 90
|
|
#define ERR_NX_WDOG_TIMER 224
|
|
#define ERR_NX_AT_FAULT 250
|
|
#define ERR_NX_INTR_SERVER 252
|
|
#define ERR_NX_UE253 253
|
|
#define ERR_NX_NO_HW 254
|
|
#define ERR_NX_HUNG_OP 255
|
|
#define ERR_NX_END 256
|
|
|
|
/* initial values for non-resume operations */
|
|
#define INIT_CRC 0 /* crc32(0L, Z_NULL, 0) */
|
|
#define INIT_ADLER 1 /* adler32(0L, Z_NULL, 0) adler is initialized to 1 */
|
|
|
|
/* prototypes */
|
|
int nxu_submit_job(struct nx_gzip_crb_cpb_t *c, void *handle);
|
|
|
|
extern void nxu_sigsegv_handler(int sig, siginfo_t *info, void *ctx);
|
|
extern int nxu_touch_pages(void *buf, long buf_len, long page_len, int wr);
|
|
|
|
/* caller supplies a print buffer 4*sizeof(crb) */
|
|
|
|
char *nx_crb_str(struct nx_gzip_crb_t *crb, char *prbuf);
|
|
char *nx_cpb_str(struct nx_gzip_cpb_t *cpb, char *prbuf);
|
|
char *nx_prt_hex(void *cp, int sz, char *prbuf);
|
|
char *nx_lzcount_str(struct nx_gzip_cpb_t *cpb, char *prbuf);
|
|
char *nx_strerror(int e);
|
|
|
|
#ifdef NX_SIM
|
|
#include <stdio.h>
|
|
int nx_sim_init(void *ctx);
|
|
int nx_sim_end(void *ctx);
|
|
int nxu_run_sim_job(struct nx_gzip_crb_cpb_t *c, void *ctx);
|
|
#endif /* NX_SIM */
|
|
|
|
/* Deflate stream manipulation */
|
|
|
|
#define set_final_bit(x) (x |= (unsigned char)1)
|
|
#define clr_final_bit(x) (x &= ~(unsigned char)1)
|
|
|
|
#define append_empty_fh_blk(p, b) do { *(p) = (2 | (1&(b))); *((p)+1) = 0; \
|
|
} while (0)
|
|
/* append 10 bits 0000001b 00...... ;
|
|
* assumes appending starts on a byte boundary; b is the final bit.
|
|
*/
|
|
|
|
|
|
#ifdef NX_842
|
|
|
|
/* 842 Engine */
|
|
|
|
struct nx_eft_crb_t {
|
|
union { /* byte[0:3] */
|
|
uint32_t eft_fc; /* bits[29-31] */
|
|
};
|
|
uint32_t reserved1; /* byte[4:7] */
|
|
union {
|
|
uint64_t csb_address; /* byte[8:15] */
|
|
struct {
|
|
uint32_t reserved2;
|
|
union {
|
|
uint32_t crb_c;
|
|
/* c==0 no ccb defined */
|
|
|
|
uint32_t crb_at;
|
|
/* at==0 address type is ignored;
|
|
* all addrs effective assumed.
|
|
*/
|
|
|
|
};
|
|
};
|
|
};
|
|
struct nx_dde_t source_dde; /* byte[16:31] */
|
|
struct nx_dde_t target_dde; /* byte[32:47] */
|
|
struct nx_ccb_t ccb; /* byte[48:63] */
|
|
union {
|
|
union nx_qw_t reserved64[3]; /* byte[64:96] */
|
|
};
|
|
struct nx_csb_t csb;
|
|
} __aligned(128);
|
|
|
|
/* 842 CRB */
|
|
|
|
#define EFT_FC_MASK size_mask(3)
|
|
#define EFT_FC_OFFSET 31
|
|
#define EFT_FC_COMPRESS 0x0
|
|
#define EFT_FC_COMPRESS_WITH_CRC 0x1
|
|
#define EFT_FC_DECOMPRESS 0x2
|
|
#define EFT_FC_DECOMPRESS_WITH_CRC 0x3
|
|
#define EFT_FC_BLK_DATA_MOVE 0x4
|
|
#endif /* NX_842 */
|
|
|
|
#endif /* _NXU_H */
|