535 lines
14 KiB
C
535 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer
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*
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* Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/ethtool.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_net.h>
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#include <linux/mfd/syscon.h>
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#include <linux/platform_device.h>
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#include <linux/stmmac.h>
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#include "stmmac_platform.h"
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#define PRG_ETH0 0x0
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#define PRG_ETH0_RGMII_MODE BIT(0)
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#define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0)
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#define PRG_ETH0_EXT_RGMII_MODE 1
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#define PRG_ETH0_EXT_RMII_MODE 4
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/* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
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#define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
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/* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
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* cycle of the 125MHz RGMII TX clock):
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* 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
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*/
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#define PRG_ETH0_TXDLY_MASK GENMASK(6, 5)
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/* divider for the result of m250_sel */
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#define PRG_ETH0_CLK_M250_DIV_SHIFT 7
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#define PRG_ETH0_CLK_M250_DIV_WIDTH 3
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#define PRG_ETH0_RGMII_TX_CLK_EN 10
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#define PRG_ETH0_INVERTED_RMII_CLK BIT(11)
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#define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12)
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/* Bypass (= 0, the signal from the GPIO input directly connects to the
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* internal sampling) or enable (= 1) the internal logic for RXEN and RXD[3:0]
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* timing tuning.
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*/
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#define PRG_ETH0_ADJ_ENABLE BIT(13)
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/* Controls whether the RXEN and RXD[3:0] signals should be aligned with the
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* input RX rising/falling edge and sent to the Ethernet internals. This sets
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* the automatically delay and skew automatically (internally).
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*/
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#define PRG_ETH0_ADJ_SETUP BIT(14)
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/* An internal counter based on the "timing-adjustment" clock. The counter is
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* cleared on both, the falling and rising edge of the RX_CLK. This selects the
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* delay (= the counter value) when to start sampling RXEN and RXD[3:0].
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*/
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#define PRG_ETH0_ADJ_DELAY GENMASK(19, 15)
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/* Adjusts the skew between each bit of RXEN and RXD[3:0]. If a signal has a
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* large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
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* ...) can be configured to be 1 to compensate for a delay of about 1ns.
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*/
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#define PRG_ETH0_ADJ_SKEW GENMASK(24, 20)
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#define PRG_ETH1 0x4
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/* Defined for adding a delay to the input RX_CLK for better timing.
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* Each step is 200ps. These bits are used with external RGMII PHYs
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* because RGMII RX only has the small window. cfg_rxclk_dly can
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* adjust the window between RX_CLK and RX_DATA and improve the stability
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* of "rx data valid".
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*/
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#define PRG_ETH1_CFG_RXCLK_DLY GENMASK(19, 16)
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struct meson8b_dwmac;
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struct meson8b_dwmac_data {
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int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
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bool has_prg_eth1_rgmii_rx_delay;
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};
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struct meson8b_dwmac {
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struct device *dev;
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void __iomem *regs;
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const struct meson8b_dwmac_data *data;
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phy_interface_t phy_mode;
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struct clk *rgmii_tx_clk;
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u32 tx_delay_ns;
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u32 rx_delay_ps;
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struct clk *timing_adj_clk;
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};
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struct meson8b_dwmac_clk_configs {
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struct clk_mux m250_mux;
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struct clk_divider m250_div;
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struct clk_fixed_factor fixed_div2;
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struct clk_gate rgmii_tx_en;
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};
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static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,
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u32 mask, u32 value)
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{
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u32 data;
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data = readl(dwmac->regs + reg);
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data &= ~mask;
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data |= (value & mask);
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writel(data, dwmac->regs + reg);
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}
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static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac,
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const char *name_suffix,
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const struct clk_parent_data *parents,
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int num_parents,
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const struct clk_ops *ops,
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struct clk_hw *hw)
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{
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struct clk_init_data init = { };
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char clk_name[32];
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snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev),
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name_suffix);
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init.name = clk_name;
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init.ops = ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_data = parents;
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init.num_parents = num_parents;
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hw->init = &init;
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return devm_clk_register(dwmac->dev, hw);
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}
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static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
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{
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struct clk *clk;
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struct device *dev = dwmac->dev;
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static const struct clk_parent_data mux_parents[] = {
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{ .fw_name = "clkin0", },
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{ .index = -1, },
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};
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static const struct clk_div_table div_table[] = {
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{ .div = 2, .val = 2, },
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{ .div = 3, .val = 3, },
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{ .div = 4, .val = 4, },
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{ .div = 5, .val = 5, },
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{ .div = 6, .val = 6, },
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{ .div = 7, .val = 7, },
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{ /* end of array */ }
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};
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struct meson8b_dwmac_clk_configs *clk_configs;
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struct clk_parent_data parent_data = { };
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clk_configs = devm_kzalloc(dev, sizeof(*clk_configs), GFP_KERNEL);
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if (!clk_configs)
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return -ENOMEM;
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clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0;
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clk_configs->m250_mux.shift = __ffs(PRG_ETH0_CLK_M250_SEL_MASK);
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clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK >>
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clk_configs->m250_mux.shift;
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clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parents,
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ARRAY_SIZE(mux_parents), &clk_mux_ops,
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&clk_configs->m250_mux.hw);
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if (WARN_ON(IS_ERR(clk)))
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return PTR_ERR(clk);
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parent_data.hw = &clk_configs->m250_mux.hw;
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clk_configs->m250_div.reg = dwmac->regs + PRG_ETH0;
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clk_configs->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT;
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clk_configs->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH;
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clk_configs->m250_div.table = div_table;
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clk_configs->m250_div.flags = CLK_DIVIDER_ALLOW_ZERO |
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CLK_DIVIDER_ROUND_CLOSEST;
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clk = meson8b_dwmac_register_clk(dwmac, "m250_div", &parent_data, 1,
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&clk_divider_ops,
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&clk_configs->m250_div.hw);
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if (WARN_ON(IS_ERR(clk)))
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return PTR_ERR(clk);
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parent_data.hw = &clk_configs->m250_div.hw;
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clk_configs->fixed_div2.mult = 1;
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clk_configs->fixed_div2.div = 2;
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clk = meson8b_dwmac_register_clk(dwmac, "fixed_div2", &parent_data, 1,
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&clk_fixed_factor_ops,
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&clk_configs->fixed_div2.hw);
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if (WARN_ON(IS_ERR(clk)))
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return PTR_ERR(clk);
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parent_data.hw = &clk_configs->fixed_div2.hw;
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clk_configs->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0;
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clk_configs->rgmii_tx_en.bit_idx = PRG_ETH0_RGMII_TX_CLK_EN;
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clk = meson8b_dwmac_register_clk(dwmac, "rgmii_tx_en", &parent_data, 1,
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&clk_gate_ops,
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&clk_configs->rgmii_tx_en.hw);
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if (WARN_ON(IS_ERR(clk)))
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return PTR_ERR(clk);
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dwmac->rgmii_tx_clk = clk;
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return 0;
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}
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static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)
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{
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switch (dwmac->phy_mode) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* enable RGMII mode */
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
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PRG_ETH0_RGMII_MODE,
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PRG_ETH0_RGMII_MODE);
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break;
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case PHY_INTERFACE_MODE_RMII:
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/* disable RGMII mode -> enables RMII mode */
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
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PRG_ETH0_RGMII_MODE, 0);
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break;
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default:
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dev_err(dwmac->dev, "fail to set phy-mode %s\n",
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phy_modes(dwmac->phy_mode));
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return -EINVAL;
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}
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return 0;
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}
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static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)
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{
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switch (dwmac->phy_mode) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* enable RGMII mode */
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
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PRG_ETH0_EXT_PHY_MODE_MASK,
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PRG_ETH0_EXT_RGMII_MODE);
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break;
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case PHY_INTERFACE_MODE_RMII:
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/* disable RGMII mode -> enables RMII mode */
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
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PRG_ETH0_EXT_PHY_MODE_MASK,
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PRG_ETH0_EXT_RMII_MODE);
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break;
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default:
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dev_err(dwmac->dev, "fail to set phy-mode %s\n",
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phy_modes(dwmac->phy_mode));
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return -EINVAL;
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}
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return 0;
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}
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static void meson8b_clk_disable_unprepare(void *data)
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{
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clk_disable_unprepare(data);
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}
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static int meson8b_devm_clk_prepare_enable(struct meson8b_dwmac *dwmac,
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struct clk *clk)
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{
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int ret;
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ret = clk_prepare_enable(clk);
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if (ret)
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return ret;
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return devm_add_action_or_reset(dwmac->dev,
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meson8b_clk_disable_unprepare, clk);
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}
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static int meson8b_init_rgmii_delays(struct meson8b_dwmac *dwmac)
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{
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u32 tx_dly_config, rx_adj_config, cfg_rxclk_dly, delay_config;
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int ret;
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rx_adj_config = 0;
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cfg_rxclk_dly = 0;
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tx_dly_config = FIELD_PREP(PRG_ETH0_TXDLY_MASK,
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dwmac->tx_delay_ns >> 1);
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if (dwmac->data->has_prg_eth1_rgmii_rx_delay)
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cfg_rxclk_dly = FIELD_PREP(PRG_ETH1_CFG_RXCLK_DLY,
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dwmac->rx_delay_ps / 200);
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else if (dwmac->rx_delay_ps == 2000)
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rx_adj_config = PRG_ETH0_ADJ_ENABLE | PRG_ETH0_ADJ_SETUP;
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switch (dwmac->phy_mode) {
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case PHY_INTERFACE_MODE_RGMII:
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delay_config = tx_dly_config | rx_adj_config;
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break;
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case PHY_INTERFACE_MODE_RGMII_RXID:
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delay_config = tx_dly_config;
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cfg_rxclk_dly = 0;
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break;
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case PHY_INTERFACE_MODE_RGMII_TXID:
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delay_config = rx_adj_config;
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break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RMII:
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delay_config = 0;
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cfg_rxclk_dly = 0;
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break;
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default:
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dev_err(dwmac->dev, "unsupported phy-mode %s\n",
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phy_modes(dwmac->phy_mode));
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return -EINVAL;
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}
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if (delay_config & PRG_ETH0_ADJ_ENABLE) {
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if (!dwmac->timing_adj_clk) {
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dev_err(dwmac->dev,
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"The timing-adjustment clock is mandatory for the RX delay re-timing\n");
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return -EINVAL;
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}
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/* The timing adjustment logic is driven by a separate clock */
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ret = meson8b_devm_clk_prepare_enable(dwmac,
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dwmac->timing_adj_clk);
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if (ret) {
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dev_err(dwmac->dev,
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"Failed to enable the timing-adjustment clock\n");
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return ret;
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}
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}
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK |
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PRG_ETH0_ADJ_ENABLE | PRG_ETH0_ADJ_SETUP |
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PRG_ETH0_ADJ_DELAY | PRG_ETH0_ADJ_SKEW,
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delay_config);
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH1, PRG_ETH1_CFG_RXCLK_DLY,
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cfg_rxclk_dly);
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return 0;
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}
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static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
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{
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int ret;
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if (phy_interface_mode_is_rgmii(dwmac->phy_mode)) {
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/* only relevant for RMII mode -> disable in RGMII mode */
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
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PRG_ETH0_INVERTED_RMII_CLK, 0);
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/* Configure the 125MHz RGMII TX clock, the IP block changes
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* the output automatically (= without us having to configure
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* a register) based on the line-speed (125MHz for Gbit speeds,
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* 25MHz for 100Mbit/s and 2.5MHz for 10Mbit/s).
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*/
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ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000);
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if (ret) {
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dev_err(dwmac->dev,
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"failed to set RGMII TX clock\n");
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return ret;
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}
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ret = meson8b_devm_clk_prepare_enable(dwmac,
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dwmac->rgmii_tx_clk);
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if (ret) {
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dev_err(dwmac->dev,
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"failed to enable the RGMII TX clock\n");
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return ret;
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}
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} else {
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/* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
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PRG_ETH0_INVERTED_RMII_CLK,
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PRG_ETH0_INVERTED_RMII_CLK);
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}
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/* enable TX_CLK and PHY_REF_CLK generator */
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meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK,
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PRG_ETH0_TX_AND_PHY_REF_CLK);
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return 0;
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}
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static int meson8b_dwmac_probe(struct platform_device *pdev)
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{
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struct plat_stmmacenet_data *plat_dat;
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struct stmmac_resources stmmac_res;
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struct meson8b_dwmac *dwmac;
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int ret;
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ret = stmmac_get_platform_resources(pdev, &stmmac_res);
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if (ret)
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return ret;
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plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
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if (IS_ERR(plat_dat))
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return PTR_ERR(plat_dat);
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dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
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if (!dwmac)
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return -ENOMEM;
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dwmac->data = (const struct meson8b_dwmac_data *)
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of_device_get_match_data(&pdev->dev);
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if (!dwmac->data)
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return -EINVAL;
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dwmac->regs = devm_platform_ioremap_resource(pdev, 1);
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if (IS_ERR(dwmac->regs))
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return PTR_ERR(dwmac->regs);
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dwmac->dev = &pdev->dev;
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ret = of_get_phy_mode(pdev->dev.of_node, &dwmac->phy_mode);
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if (ret) {
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dev_err(&pdev->dev, "missing phy-mode property\n");
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return ret;
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}
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/* use 2ns as fallback since this value was previously hardcoded */
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if (of_property_read_u32(pdev->dev.of_node, "amlogic,tx-delay-ns",
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&dwmac->tx_delay_ns))
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dwmac->tx_delay_ns = 2;
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/* RX delay defaults to 0ps since this is what many boards use */
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if (of_property_read_u32(pdev->dev.of_node, "rx-internal-delay-ps",
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&dwmac->rx_delay_ps)) {
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if (!of_property_read_u32(pdev->dev.of_node,
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"amlogic,rx-delay-ns",
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&dwmac->rx_delay_ps))
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/* convert ns to ps */
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dwmac->rx_delay_ps *= 1000;
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}
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if (dwmac->data->has_prg_eth1_rgmii_rx_delay) {
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if (dwmac->rx_delay_ps > 3000 || dwmac->rx_delay_ps % 200) {
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dev_err(dwmac->dev,
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"The RGMII RX delay range is 0..3000ps in 200ps steps");
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return -EINVAL;
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}
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} else {
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if (dwmac->rx_delay_ps != 0 && dwmac->rx_delay_ps != 2000) {
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dev_err(dwmac->dev,
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"The only allowed RGMII RX delays values are: 0ps, 2000ps");
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return -EINVAL;
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}
|
|
}
|
|
|
|
dwmac->timing_adj_clk = devm_clk_get_optional(dwmac->dev,
|
|
"timing-adjustment");
|
|
if (IS_ERR(dwmac->timing_adj_clk))
|
|
return PTR_ERR(dwmac->timing_adj_clk);
|
|
|
|
ret = meson8b_init_rgmii_delays(dwmac);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = meson8b_init_rgmii_tx_clk(dwmac);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = dwmac->data->set_phy_mode(dwmac);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = meson8b_init_prg_eth(dwmac);
|
|
if (ret)
|
|
return ret;
|
|
|
|
plat_dat->bsp_priv = dwmac;
|
|
|
|
return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
|
|
}
|
|
|
|
static const struct meson8b_dwmac_data meson8b_dwmac_data = {
|
|
.set_phy_mode = meson8b_set_phy_mode,
|
|
.has_prg_eth1_rgmii_rx_delay = false,
|
|
};
|
|
|
|
static const struct meson8b_dwmac_data meson_axg_dwmac_data = {
|
|
.set_phy_mode = meson_axg_set_phy_mode,
|
|
.has_prg_eth1_rgmii_rx_delay = false,
|
|
};
|
|
|
|
static const struct meson8b_dwmac_data meson_g12a_dwmac_data = {
|
|
.set_phy_mode = meson_axg_set_phy_mode,
|
|
.has_prg_eth1_rgmii_rx_delay = true,
|
|
};
|
|
|
|
static const struct of_device_id meson8b_dwmac_match[] = {
|
|
{
|
|
.compatible = "amlogic,meson8b-dwmac",
|
|
.data = &meson8b_dwmac_data,
|
|
},
|
|
{
|
|
.compatible = "amlogic,meson8m2-dwmac",
|
|
.data = &meson8b_dwmac_data,
|
|
},
|
|
{
|
|
.compatible = "amlogic,meson-gxbb-dwmac",
|
|
.data = &meson8b_dwmac_data,
|
|
},
|
|
{
|
|
.compatible = "amlogic,meson-axg-dwmac",
|
|
.data = &meson_axg_dwmac_data,
|
|
},
|
|
{
|
|
.compatible = "amlogic,meson-g12a-dwmac",
|
|
.data = &meson_g12a_dwmac_data,
|
|
},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
|
|
|
|
static struct platform_driver meson8b_dwmac_driver = {
|
|
.probe = meson8b_dwmac_probe,
|
|
.remove_new = stmmac_pltfr_remove,
|
|
.driver = {
|
|
.name = "meson8b-dwmac",
|
|
.pm = &stmmac_pltfr_pm_ops,
|
|
.of_match_table = meson8b_dwmac_match,
|
|
},
|
|
};
|
|
module_platform_driver(meson8b_dwmac_driver);
|
|
|
|
MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
|
|
MODULE_DESCRIPTION("Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer");
|
|
MODULE_LICENSE("GPL v2");
|