1138 lines
31 KiB
C
1138 lines
31 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/sfp.h>
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#include "ionic.h"
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#include "ionic_bus.h"
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#include "ionic_lif.h"
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#include "ionic_ethtool.h"
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#include "ionic_stats.h"
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#define IONIC_MAX_RX_COPYBREAK min(U16_MAX, IONIC_MAX_BUF_LEN)
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static void ionic_get_stats_strings(struct ionic_lif *lif, u8 *buf)
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{
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u32 i;
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for (i = 0; i < ionic_num_stats_grps; i++)
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ionic_stats_groups[i].get_strings(lif, &buf);
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}
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static void ionic_get_stats(struct net_device *netdev,
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struct ethtool_stats *stats, u64 *buf)
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{
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struct ionic_lif *lif = netdev_priv(netdev);
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u32 i;
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if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
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return;
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memset(buf, 0, stats->n_stats * sizeof(*buf));
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for (i = 0; i < ionic_num_stats_grps; i++)
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ionic_stats_groups[i].get_values(lif, &buf);
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}
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static int ionic_get_stats_count(struct ionic_lif *lif)
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{
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int i, num_stats = 0;
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for (i = 0; i < ionic_num_stats_grps; i++)
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num_stats += ionic_stats_groups[i].get_count(lif);
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return num_stats;
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}
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static int ionic_get_sset_count(struct net_device *netdev, int sset)
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{
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struct ionic_lif *lif = netdev_priv(netdev);
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int count = 0;
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switch (sset) {
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case ETH_SS_STATS:
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count = ionic_get_stats_count(lif);
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break;
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}
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return count;
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}
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static void ionic_get_strings(struct net_device *netdev,
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u32 sset, u8 *buf)
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{
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struct ionic_lif *lif = netdev_priv(netdev);
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switch (sset) {
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case ETH_SS_STATS:
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ionic_get_stats_strings(lif, buf);
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break;
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}
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}
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static void ionic_get_drvinfo(struct net_device *netdev,
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struct ethtool_drvinfo *drvinfo)
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{
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struct ionic_lif *lif = netdev_priv(netdev);
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struct ionic *ionic = lif->ionic;
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strscpy(drvinfo->driver, IONIC_DRV_NAME, sizeof(drvinfo->driver));
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strscpy(drvinfo->fw_version, ionic->idev.dev_info.fw_version,
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sizeof(drvinfo->fw_version));
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strscpy(drvinfo->bus_info, ionic_bus_info(ionic),
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sizeof(drvinfo->bus_info));
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}
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static int ionic_get_regs_len(struct net_device *netdev)
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{
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return (IONIC_DEV_INFO_REG_COUNT + IONIC_DEV_CMD_REG_COUNT) * sizeof(u32);
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}
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static void ionic_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
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void *p)
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{
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struct ionic_lif *lif = netdev_priv(netdev);
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struct ionic_dev *idev;
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unsigned int offset;
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unsigned int size;
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regs->version = IONIC_DEV_CMD_REG_VERSION;
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idev = &lif->ionic->idev;
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if (!idev->dev_info_regs)
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return;
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offset = 0;
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size = IONIC_DEV_INFO_REG_COUNT * sizeof(u32);
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memcpy_fromio(p + offset, lif->ionic->idev.dev_info_regs->words, size);
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offset += size;
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size = IONIC_DEV_CMD_REG_COUNT * sizeof(u32);
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memcpy_fromio(p + offset, idev->dev_cmd_regs->words, size);
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}
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static void ionic_get_link_ext_stats(struct net_device *netdev,
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struct ethtool_link_ext_stats *stats)
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{
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struct ionic_lif *lif = netdev_priv(netdev);
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if (lif->ionic->pdev->is_physfn)
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stats->link_down_events = lif->link_down_count;
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}
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static int ionic_get_link_ksettings(struct net_device *netdev,
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struct ethtool_link_ksettings *ks)
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{
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struct ionic_lif *lif = netdev_priv(netdev);
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struct ionic_dev *idev = &lif->ionic->idev;
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int copper_seen = 0;
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ethtool_link_ksettings_zero_link_mode(ks, supported);
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if (!idev->port_info) {
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netdev_err(netdev, "port_info not initialized\n");
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return -EOPNOTSUPP;
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}
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/* The port_info data is found in a DMA space that the NIC keeps
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* up-to-date, so there's no need to request the data from the
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* NIC, we already have it in our memory space.
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*/
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switch (le16_to_cpu(idev->port_info->status.xcvr.pid)) {
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/* Copper */
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case IONIC_XCVR_PID_QSFP_100G_CR4:
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ethtool_link_ksettings_add_link_mode(ks, supported,
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100000baseCR4_Full);
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copper_seen++;
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break;
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case IONIC_XCVR_PID_QSFP_40GBASE_CR4:
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ethtool_link_ksettings_add_link_mode(ks, supported,
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40000baseCR4_Full);
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copper_seen++;
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break;
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case IONIC_XCVR_PID_SFP_25GBASE_CR_S:
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case IONIC_XCVR_PID_SFP_25GBASE_CR_L:
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case IONIC_XCVR_PID_SFP_25GBASE_CR_N:
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ethtool_link_ksettings_add_link_mode(ks, supported,
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25000baseCR_Full);
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copper_seen++;
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break;
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case IONIC_XCVR_PID_SFP_10GBASE_AOC:
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case IONIC_XCVR_PID_SFP_10GBASE_CU:
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ethtool_link_ksettings_add_link_mode(ks, supported,
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10000baseCR_Full);
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copper_seen++;
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break;
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/* Fibre */
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case IONIC_XCVR_PID_QSFP_100G_SR4:
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case IONIC_XCVR_PID_QSFP_100G_AOC:
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ethtool_link_ksettings_add_link_mode(ks, supported,
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100000baseSR4_Full);
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break;
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case IONIC_XCVR_PID_QSFP_100G_CWDM4:
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case IONIC_XCVR_PID_QSFP_100G_PSM4:
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case IONIC_XCVR_PID_QSFP_100G_LR4:
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ethtool_link_ksettings_add_link_mode(ks, supported,
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100000baseLR4_ER4_Full);
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break;
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case IONIC_XCVR_PID_QSFP_100G_ER4:
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ethtool_link_ksettings_add_link_mode(ks, supported,
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100000baseLR4_ER4_Full);
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break;
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case IONIC_XCVR_PID_QSFP_40GBASE_SR4:
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case IONIC_XCVR_PID_QSFP_40GBASE_AOC:
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ethtool_link_ksettings_add_link_mode(ks, supported,
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40000baseSR4_Full);
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break;
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case IONIC_XCVR_PID_QSFP_40GBASE_LR4:
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ethtool_link_ksettings_add_link_mode(ks, supported,
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40000baseLR4_Full);
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break;
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case IONIC_XCVR_PID_SFP_25GBASE_SR:
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case IONIC_XCVR_PID_SFP_25GBASE_AOC:
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case IONIC_XCVR_PID_SFP_25GBASE_ACC:
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ethtool_link_ksettings_add_link_mode(ks, supported,
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25000baseSR_Full);
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break;
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case IONIC_XCVR_PID_SFP_10GBASE_SR:
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ethtool_link_ksettings_add_link_mode(ks, supported,
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10000baseSR_Full);
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break;
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case IONIC_XCVR_PID_SFP_10GBASE_LR:
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ethtool_link_ksettings_add_link_mode(ks, supported,
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10000baseLR_Full);
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break;
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case IONIC_XCVR_PID_SFP_10GBASE_LRM:
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ethtool_link_ksettings_add_link_mode(ks, supported,
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10000baseLRM_Full);
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break;
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case IONIC_XCVR_PID_SFP_10GBASE_ER:
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ethtool_link_ksettings_add_link_mode(ks, supported,
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10000baseER_Full);
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break;
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case IONIC_XCVR_PID_SFP_10GBASE_T:
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ethtool_link_ksettings_add_link_mode(ks, supported,
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10000baseT_Full);
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break;
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case IONIC_XCVR_PID_SFP_1000BASE_T:
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ethtool_link_ksettings_add_link_mode(ks, supported,
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1000baseT_Full);
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break;
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case IONIC_XCVR_PID_UNKNOWN:
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/* This means there's no module plugged in */
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break;
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default:
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dev_info(lif->ionic->dev, "unknown xcvr type pid=%d / 0x%x\n",
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idev->port_info->status.xcvr.pid,
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idev->port_info->status.xcvr.pid);
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break;
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}
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linkmode_copy(ks->link_modes.advertising, ks->link_modes.supported);
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ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER);
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ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS);
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if (idev->port_info->config.fec_type == IONIC_PORT_FEC_TYPE_FC)
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ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_BASER);
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else if (idev->port_info->config.fec_type == IONIC_PORT_FEC_TYPE_RS)
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ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS);
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ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE);
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ethtool_link_ksettings_add_link_mode(ks, supported, Pause);
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if (idev->port_info->status.xcvr.phy == IONIC_PHY_TYPE_COPPER ||
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copper_seen)
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ks->base.port = PORT_DA;
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else if (idev->port_info->status.xcvr.phy == IONIC_PHY_TYPE_FIBER)
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ks->base.port = PORT_FIBRE;
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else
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ks->base.port = PORT_NONE;
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if (ks->base.port != PORT_NONE) {
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ks->base.speed = le32_to_cpu(lif->info->status.link_speed);
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if (le16_to_cpu(lif->info->status.link_status))
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ks->base.duplex = DUPLEX_FULL;
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else
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ks->base.duplex = DUPLEX_UNKNOWN;
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ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
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if (idev->port_info->config.an_enable) {
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ethtool_link_ksettings_add_link_mode(ks, advertising,
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Autoneg);
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ks->base.autoneg = AUTONEG_ENABLE;
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}
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}
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return 0;
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}
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static int ionic_set_link_ksettings(struct net_device *netdev,
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const struct ethtool_link_ksettings *ks)
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{
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struct ionic_lif *lif = netdev_priv(netdev);
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struct ionic_dev *idev = &lif->ionic->idev;
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struct ionic *ionic = lif->ionic;
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int err = 0;
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if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
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return -EBUSY;
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/* set autoneg */
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if (ks->base.autoneg != idev->port_info->config.an_enable) {
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mutex_lock(&ionic->dev_cmd_lock);
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ionic_dev_cmd_port_autoneg(idev, ks->base.autoneg);
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err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
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mutex_unlock(&ionic->dev_cmd_lock);
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if (err)
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return err;
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}
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/* set speed */
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if (ks->base.speed != le32_to_cpu(idev->port_info->config.speed)) {
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mutex_lock(&ionic->dev_cmd_lock);
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ionic_dev_cmd_port_speed(idev, ks->base.speed);
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err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
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mutex_unlock(&ionic->dev_cmd_lock);
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if (err)
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return err;
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}
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return 0;
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}
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static void ionic_get_pauseparam(struct net_device *netdev,
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struct ethtool_pauseparam *pause)
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{
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struct ionic_lif *lif = netdev_priv(netdev);
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u8 pause_type;
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pause->autoneg = 0;
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pause_type = lif->ionic->idev.port_info->config.pause_type;
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if (pause_type) {
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pause->rx_pause = (pause_type & IONIC_PAUSE_F_RX) ? 1 : 0;
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pause->tx_pause = (pause_type & IONIC_PAUSE_F_TX) ? 1 : 0;
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}
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}
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static int ionic_set_pauseparam(struct net_device *netdev,
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struct ethtool_pauseparam *pause)
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{
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struct ionic_lif *lif = netdev_priv(netdev);
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struct ionic *ionic = lif->ionic;
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u32 requested_pause;
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int err;
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if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
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return -EBUSY;
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if (pause->autoneg)
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return -EOPNOTSUPP;
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/* change both at the same time */
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requested_pause = IONIC_PORT_PAUSE_TYPE_LINK;
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if (pause->rx_pause)
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requested_pause |= IONIC_PAUSE_F_RX;
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if (pause->tx_pause)
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requested_pause |= IONIC_PAUSE_F_TX;
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if (requested_pause == lif->ionic->idev.port_info->config.pause_type)
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return 0;
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mutex_lock(&ionic->dev_cmd_lock);
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ionic_dev_cmd_port_pause(&lif->ionic->idev, requested_pause);
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err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
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mutex_unlock(&ionic->dev_cmd_lock);
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if (err)
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return err;
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return 0;
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}
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static int ionic_get_fecparam(struct net_device *netdev,
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struct ethtool_fecparam *fec)
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{
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struct ionic_lif *lif = netdev_priv(netdev);
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switch (lif->ionic->idev.port_info->config.fec_type) {
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case IONIC_PORT_FEC_TYPE_NONE:
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fec->active_fec = ETHTOOL_FEC_OFF;
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break;
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case IONIC_PORT_FEC_TYPE_RS:
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fec->active_fec = ETHTOOL_FEC_RS;
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break;
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case IONIC_PORT_FEC_TYPE_FC:
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fec->active_fec = ETHTOOL_FEC_BASER;
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break;
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}
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fec->fec = ETHTOOL_FEC_OFF | ETHTOOL_FEC_RS | ETHTOOL_FEC_BASER;
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return 0;
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}
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static int ionic_set_fecparam(struct net_device *netdev,
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struct ethtool_fecparam *fec)
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{
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struct ionic_lif *lif = netdev_priv(netdev);
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u8 fec_type;
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int ret = 0;
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if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
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return -EBUSY;
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if (lif->ionic->idev.port_info->config.an_enable) {
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netdev_err(netdev, "FEC request not allowed while autoneg is enabled\n");
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return -EINVAL;
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}
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switch (fec->fec) {
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case ETHTOOL_FEC_NONE:
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fec_type = IONIC_PORT_FEC_TYPE_NONE;
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break;
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case ETHTOOL_FEC_OFF:
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fec_type = IONIC_PORT_FEC_TYPE_NONE;
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break;
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case ETHTOOL_FEC_RS:
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fec_type = IONIC_PORT_FEC_TYPE_RS;
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break;
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case ETHTOOL_FEC_BASER:
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fec_type = IONIC_PORT_FEC_TYPE_FC;
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break;
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case ETHTOOL_FEC_AUTO:
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default:
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netdev_err(netdev, "FEC request 0x%04x not supported\n",
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fec->fec);
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return -EINVAL;
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}
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if (fec_type != lif->ionic->idev.port_info->config.fec_type) {
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mutex_lock(&lif->ionic->dev_cmd_lock);
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ionic_dev_cmd_port_fec(&lif->ionic->idev, fec_type);
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ret = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
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mutex_unlock(&lif->ionic->dev_cmd_lock);
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}
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return ret;
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}
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static int ionic_get_coalesce(struct net_device *netdev,
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struct ethtool_coalesce *coalesce,
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struct kernel_ethtool_coalesce *kernel_coal,
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struct netlink_ext_ack *extack)
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{
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struct ionic_lif *lif = netdev_priv(netdev);
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coalesce->tx_coalesce_usecs = lif->tx_coalesce_usecs;
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coalesce->rx_coalesce_usecs = lif->rx_coalesce_usecs;
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if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
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coalesce->use_adaptive_tx_coalesce = test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state);
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else
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coalesce->use_adaptive_tx_coalesce = 0;
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coalesce->use_adaptive_rx_coalesce = test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state);
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return 0;
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}
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static int ionic_set_coalesce(struct net_device *netdev,
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struct ethtool_coalesce *coalesce,
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struct kernel_ethtool_coalesce *kernel_coal,
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struct netlink_ext_ack *extack)
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{
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struct ionic_lif *lif = netdev_priv(netdev);
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struct ionic_identity *ident;
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u32 rx_coal, rx_dim;
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u32 tx_coal, tx_dim;
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unsigned int i;
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ident = &lif->ionic->ident;
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if (ident->dev.intr_coal_div == 0) {
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netdev_warn(netdev, "bad HW value in dev.intr_coal_div = %d\n",
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ident->dev.intr_coal_div);
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return -EIO;
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}
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/* Tx normally shares Rx interrupt, so only change Rx if not split */
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if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) &&
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(coalesce->tx_coalesce_usecs != lif->rx_coalesce_usecs ||
|
|
coalesce->use_adaptive_tx_coalesce)) {
|
|
netdev_warn(netdev, "only rx parameters can be changed\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Convert the usec request to a HW usable value. If they asked
|
|
* for non-zero and it resolved to zero, bump it up
|
|
*/
|
|
rx_coal = ionic_coal_usec_to_hw(lif->ionic, coalesce->rx_coalesce_usecs);
|
|
if (!rx_coal && coalesce->rx_coalesce_usecs)
|
|
rx_coal = 1;
|
|
tx_coal = ionic_coal_usec_to_hw(lif->ionic, coalesce->tx_coalesce_usecs);
|
|
if (!tx_coal && coalesce->tx_coalesce_usecs)
|
|
tx_coal = 1;
|
|
|
|
if (rx_coal > IONIC_INTR_CTRL_COAL_MAX ||
|
|
tx_coal > IONIC_INTR_CTRL_COAL_MAX)
|
|
return -ERANGE;
|
|
|
|
/* Save the new values */
|
|
lif->rx_coalesce_usecs = coalesce->rx_coalesce_usecs;
|
|
lif->rx_coalesce_hw = rx_coal;
|
|
|
|
if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
|
|
lif->tx_coalesce_usecs = coalesce->tx_coalesce_usecs;
|
|
else
|
|
lif->tx_coalesce_usecs = coalesce->rx_coalesce_usecs;
|
|
lif->tx_coalesce_hw = tx_coal;
|
|
|
|
if (coalesce->use_adaptive_rx_coalesce) {
|
|
set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state);
|
|
rx_dim = rx_coal;
|
|
} else {
|
|
clear_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state);
|
|
rx_dim = 0;
|
|
}
|
|
|
|
if (coalesce->use_adaptive_tx_coalesce) {
|
|
set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state);
|
|
tx_dim = tx_coal;
|
|
} else {
|
|
clear_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state);
|
|
tx_dim = 0;
|
|
}
|
|
|
|
if (test_bit(IONIC_LIF_F_UP, lif->state)) {
|
|
for (i = 0; i < lif->nxqs; i++) {
|
|
if (lif->rxqcqs[i]->flags & IONIC_QCQ_F_INTR) {
|
|
ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
|
|
lif->rxqcqs[i]->intr.index,
|
|
lif->rx_coalesce_hw);
|
|
lif->rxqcqs[i]->intr.dim_coal_hw = rx_dim;
|
|
}
|
|
|
|
if (lif->txqcqs[i]->flags & IONIC_QCQ_F_INTR) {
|
|
ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
|
|
lif->txqcqs[i]->intr.index,
|
|
lif->tx_coalesce_hw);
|
|
lif->txqcqs[i]->intr.dim_coal_hw = tx_dim;
|
|
}
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ionic_validate_cmb_config(struct ionic_lif *lif,
|
|
struct ionic_queue_params *qparam)
|
|
{
|
|
int pages_have, pages_required = 0;
|
|
unsigned long sz;
|
|
|
|
if (!lif->ionic->idev.cmb_inuse &&
|
|
(qparam->cmb_tx || qparam->cmb_rx)) {
|
|
netdev_info(lif->netdev, "CMB rings are not supported on this device\n");
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
if (qparam->cmb_tx) {
|
|
if (!(lif->qtype_info[IONIC_QTYPE_TXQ].features & IONIC_QIDENT_F_CMB)) {
|
|
netdev_info(lif->netdev,
|
|
"CMB rings for tx-push are not supported on this device\n");
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
sz = sizeof(struct ionic_txq_desc) * qparam->ntxq_descs * qparam->nxqs;
|
|
pages_required += ALIGN(sz, PAGE_SIZE) / PAGE_SIZE;
|
|
}
|
|
|
|
if (qparam->cmb_rx) {
|
|
if (!(lif->qtype_info[IONIC_QTYPE_RXQ].features & IONIC_QIDENT_F_CMB)) {
|
|
netdev_info(lif->netdev,
|
|
"CMB rings for rx-push are not supported on this device\n");
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
sz = sizeof(struct ionic_rxq_desc) * qparam->nrxq_descs * qparam->nxqs;
|
|
pages_required += ALIGN(sz, PAGE_SIZE) / PAGE_SIZE;
|
|
}
|
|
|
|
pages_have = lif->ionic->bars[IONIC_PCI_BAR_CMB].len / PAGE_SIZE;
|
|
if (pages_required > pages_have) {
|
|
netdev_info(lif->netdev,
|
|
"Not enough CMB pages for number of queues and size of descriptor rings, need %d have %d",
|
|
pages_required, pages_have);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
return pages_required;
|
|
}
|
|
|
|
static int ionic_cmb_rings_toggle(struct ionic_lif *lif, bool cmb_tx, bool cmb_rx)
|
|
{
|
|
struct ionic_queue_params qparam;
|
|
int pages_used;
|
|
|
|
if (netif_running(lif->netdev)) {
|
|
netdev_info(lif->netdev, "Please stop device to toggle CMB for tx/rx-push\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
ionic_init_queue_params(lif, &qparam);
|
|
qparam.cmb_tx = cmb_tx;
|
|
qparam.cmb_rx = cmb_rx;
|
|
pages_used = ionic_validate_cmb_config(lif, &qparam);
|
|
if (pages_used < 0)
|
|
return pages_used;
|
|
|
|
if (cmb_tx)
|
|
set_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state);
|
|
else
|
|
clear_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state);
|
|
|
|
if (cmb_rx)
|
|
set_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state);
|
|
else
|
|
clear_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state);
|
|
|
|
if (cmb_tx || cmb_rx)
|
|
netdev_info(lif->netdev, "Enabling CMB %s %s rings - %d pages\n",
|
|
cmb_tx ? "TX" : "", cmb_rx ? "RX" : "", pages_used);
|
|
else
|
|
netdev_info(lif->netdev, "Disabling CMB rings\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ionic_get_ringparam(struct net_device *netdev,
|
|
struct ethtool_ringparam *ring,
|
|
struct kernel_ethtool_ringparam *kernel_ring,
|
|
struct netlink_ext_ack *extack)
|
|
{
|
|
struct ionic_lif *lif = netdev_priv(netdev);
|
|
|
|
ring->tx_max_pending = IONIC_MAX_TX_DESC;
|
|
ring->tx_pending = lif->ntxq_descs;
|
|
ring->rx_max_pending = IONIC_MAX_RX_DESC;
|
|
ring->rx_pending = lif->nrxq_descs;
|
|
kernel_ring->tx_push = test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state);
|
|
kernel_ring->rx_push = test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state);
|
|
}
|
|
|
|
static int ionic_set_ringparam(struct net_device *netdev,
|
|
struct ethtool_ringparam *ring,
|
|
struct kernel_ethtool_ringparam *kernel_ring,
|
|
struct netlink_ext_ack *extack)
|
|
{
|
|
struct ionic_lif *lif = netdev_priv(netdev);
|
|
struct ionic_queue_params qparam;
|
|
int err;
|
|
|
|
if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
|
|
return -EBUSY;
|
|
|
|
ionic_init_queue_params(lif, &qparam);
|
|
|
|
if (ring->rx_mini_pending || ring->rx_jumbo_pending) {
|
|
netdev_info(netdev, "Changing jumbo or mini descriptors not supported\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (!is_power_of_2(ring->tx_pending) ||
|
|
!is_power_of_2(ring->rx_pending)) {
|
|
netdev_info(netdev, "Descriptor count must be a power of 2\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* if nothing to do return success */
|
|
if (ring->tx_pending == lif->ntxq_descs &&
|
|
ring->rx_pending == lif->nrxq_descs &&
|
|
kernel_ring->tx_push == test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) &&
|
|
kernel_ring->rx_push == test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state))
|
|
return 0;
|
|
|
|
qparam.ntxq_descs = ring->tx_pending;
|
|
qparam.nrxq_descs = ring->rx_pending;
|
|
qparam.cmb_tx = kernel_ring->tx_push;
|
|
qparam.cmb_rx = kernel_ring->rx_push;
|
|
|
|
err = ionic_validate_cmb_config(lif, &qparam);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
if (kernel_ring->tx_push != test_bit(IONIC_LIF_F_CMB_TX_RINGS, lif->state) ||
|
|
kernel_ring->rx_push != test_bit(IONIC_LIF_F_CMB_RX_RINGS, lif->state)) {
|
|
err = ionic_cmb_rings_toggle(lif, kernel_ring->tx_push,
|
|
kernel_ring->rx_push);
|
|
if (err < 0)
|
|
return err;
|
|
}
|
|
|
|
if (ring->tx_pending != lif->ntxq_descs)
|
|
netdev_info(netdev, "Changing Tx ring size from %d to %d\n",
|
|
lif->ntxq_descs, ring->tx_pending);
|
|
|
|
if (ring->rx_pending != lif->nrxq_descs)
|
|
netdev_info(netdev, "Changing Rx ring size from %d to %d\n",
|
|
lif->nrxq_descs, ring->rx_pending);
|
|
|
|
/* if we're not running, just set the values and return */
|
|
if (!netif_running(lif->netdev)) {
|
|
lif->ntxq_descs = ring->tx_pending;
|
|
lif->nrxq_descs = ring->rx_pending;
|
|
return 0;
|
|
}
|
|
|
|
mutex_lock(&lif->queue_lock);
|
|
err = ionic_reconfigure_queues(lif, &qparam);
|
|
mutex_unlock(&lif->queue_lock);
|
|
if (err)
|
|
netdev_info(netdev, "Ring reconfiguration failed, changes canceled: %d\n", err);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void ionic_get_channels(struct net_device *netdev,
|
|
struct ethtool_channels *ch)
|
|
{
|
|
struct ionic_lif *lif = netdev_priv(netdev);
|
|
|
|
/* report maximum channels */
|
|
ch->max_combined = lif->ionic->ntxqs_per_lif;
|
|
ch->max_rx = lif->ionic->ntxqs_per_lif / 2;
|
|
ch->max_tx = lif->ionic->ntxqs_per_lif / 2;
|
|
|
|
/* report current channels */
|
|
if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) {
|
|
ch->rx_count = lif->nxqs;
|
|
ch->tx_count = lif->nxqs;
|
|
} else {
|
|
ch->combined_count = lif->nxqs;
|
|
}
|
|
}
|
|
|
|
static int ionic_set_channels(struct net_device *netdev,
|
|
struct ethtool_channels *ch)
|
|
{
|
|
struct ionic_lif *lif = netdev_priv(netdev);
|
|
struct ionic_queue_params qparam;
|
|
int max_cnt;
|
|
int err;
|
|
|
|
if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
|
|
return -EBUSY;
|
|
|
|
ionic_init_queue_params(lif, &qparam);
|
|
|
|
if ((ch->rx_count || ch->tx_count) && lif->xdp_prog) {
|
|
netdev_info(lif->netdev, "Split Tx/Rx interrupts not available when using XDP\n");
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
if (ch->rx_count != ch->tx_count) {
|
|
netdev_info(netdev, "The rx and tx count must be equal\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (ch->combined_count && ch->rx_count) {
|
|
netdev_info(netdev, "Use either combined or rx and tx, not both\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
max_cnt = lif->ionic->ntxqs_per_lif;
|
|
if (ch->combined_count) {
|
|
if (ch->combined_count > max_cnt)
|
|
return -EINVAL;
|
|
|
|
if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
|
|
netdev_info(lif->netdev, "Sharing queue interrupts\n");
|
|
else if (ch->combined_count == lif->nxqs)
|
|
return 0;
|
|
|
|
if (lif->nxqs != ch->combined_count)
|
|
netdev_info(netdev, "Changing queue count from %d to %d\n",
|
|
lif->nxqs, ch->combined_count);
|
|
|
|
qparam.nxqs = ch->combined_count;
|
|
qparam.intr_split = false;
|
|
} else {
|
|
max_cnt /= 2;
|
|
if (ch->rx_count > max_cnt)
|
|
return -EINVAL;
|
|
|
|
if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
|
|
netdev_info(lif->netdev, "Splitting queue interrupts\n");
|
|
else if (ch->rx_count == lif->nxqs)
|
|
return 0;
|
|
|
|
if (lif->nxqs != ch->rx_count)
|
|
netdev_info(netdev, "Changing queue count from %d to %d\n",
|
|
lif->nxqs, ch->rx_count);
|
|
|
|
qparam.nxqs = ch->rx_count;
|
|
qparam.intr_split = true;
|
|
}
|
|
|
|
err = ionic_validate_cmb_config(lif, &qparam);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
/* if we're not running, just set the values and return */
|
|
if (!netif_running(lif->netdev)) {
|
|
lif->nxqs = qparam.nxqs;
|
|
|
|
if (qparam.intr_split) {
|
|
set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
|
|
} else {
|
|
clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
|
|
lif->tx_coalesce_usecs = lif->rx_coalesce_usecs;
|
|
lif->tx_coalesce_hw = lif->rx_coalesce_hw;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
mutex_lock(&lif->queue_lock);
|
|
err = ionic_reconfigure_queues(lif, &qparam);
|
|
mutex_unlock(&lif->queue_lock);
|
|
if (err)
|
|
netdev_info(netdev, "Queue reconfiguration failed, changes canceled: %d\n", err);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int ionic_get_rxnfc(struct net_device *netdev,
|
|
struct ethtool_rxnfc *info, u32 *rules)
|
|
{
|
|
struct ionic_lif *lif = netdev_priv(netdev);
|
|
int err = 0;
|
|
|
|
switch (info->cmd) {
|
|
case ETHTOOL_GRXRINGS:
|
|
info->data = lif->nxqs;
|
|
break;
|
|
default:
|
|
netdev_dbg(netdev, "Command parameter %d is not supported\n",
|
|
info->cmd);
|
|
err = -EOPNOTSUPP;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static u32 ionic_get_rxfh_indir_size(struct net_device *netdev)
|
|
{
|
|
struct ionic_lif *lif = netdev_priv(netdev);
|
|
|
|
return le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
|
|
}
|
|
|
|
static u32 ionic_get_rxfh_key_size(struct net_device *netdev)
|
|
{
|
|
return IONIC_RSS_HASH_KEY_SIZE;
|
|
}
|
|
|
|
static int ionic_get_rxfh(struct net_device *netdev,
|
|
struct ethtool_rxfh_param *rxfh)
|
|
{
|
|
struct ionic_lif *lif = netdev_priv(netdev);
|
|
unsigned int i, tbl_sz;
|
|
|
|
if (rxfh->indir) {
|
|
tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
|
|
for (i = 0; i < tbl_sz; i++)
|
|
rxfh->indir[i] = lif->rss_ind_tbl[i];
|
|
}
|
|
|
|
if (rxfh->key)
|
|
memcpy(rxfh->key, lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE);
|
|
|
|
rxfh->hfunc = ETH_RSS_HASH_TOP;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ionic_set_rxfh(struct net_device *netdev,
|
|
struct ethtool_rxfh_param *rxfh,
|
|
struct netlink_ext_ack *extack)
|
|
{
|
|
struct ionic_lif *lif = netdev_priv(netdev);
|
|
|
|
if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE &&
|
|
rxfh->hfunc != ETH_RSS_HASH_TOP)
|
|
return -EOPNOTSUPP;
|
|
|
|
return ionic_lif_rss_config(lif, lif->rss_types,
|
|
rxfh->key, rxfh->indir);
|
|
}
|
|
|
|
static int ionic_set_tunable(struct net_device *dev,
|
|
const struct ethtool_tunable *tuna,
|
|
const void *data)
|
|
{
|
|
struct ionic_lif *lif = netdev_priv(dev);
|
|
u32 rx_copybreak;
|
|
|
|
switch (tuna->id) {
|
|
case ETHTOOL_RX_COPYBREAK:
|
|
rx_copybreak = *(u32 *)data;
|
|
if (rx_copybreak > IONIC_MAX_RX_COPYBREAK) {
|
|
netdev_err(dev, "Max supported rx_copybreak size: %u\n",
|
|
IONIC_MAX_RX_COPYBREAK);
|
|
return -EINVAL;
|
|
}
|
|
lif->rx_copybreak = (u16)rx_copybreak;
|
|
break;
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ionic_get_tunable(struct net_device *netdev,
|
|
const struct ethtool_tunable *tuna, void *data)
|
|
{
|
|
struct ionic_lif *lif = netdev_priv(netdev);
|
|
|
|
switch (tuna->id) {
|
|
case ETHTOOL_RX_COPYBREAK:
|
|
*(u32 *)data = lif->rx_copybreak;
|
|
break;
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ionic_get_module_info(struct net_device *netdev,
|
|
struct ethtool_modinfo *modinfo)
|
|
|
|
{
|
|
struct ionic_lif *lif = netdev_priv(netdev);
|
|
struct ionic_dev *idev = &lif->ionic->idev;
|
|
struct ionic_xcvr_status *xcvr;
|
|
struct sfp_eeprom_base *sfp;
|
|
|
|
xcvr = &idev->port_info->status.xcvr;
|
|
sfp = (struct sfp_eeprom_base *) xcvr->sprom;
|
|
|
|
/* report the module data type and length */
|
|
switch (sfp->phys_id) {
|
|
case SFF8024_ID_SFP:
|
|
modinfo->type = ETH_MODULE_SFF_8079;
|
|
modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
|
|
break;
|
|
case SFF8024_ID_QSFP_8436_8636:
|
|
case SFF8024_ID_QSFP28_8636:
|
|
modinfo->type = ETH_MODULE_SFF_8436;
|
|
modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
|
|
break;
|
|
default:
|
|
netdev_info(netdev, "unknown xcvr type 0x%02x\n",
|
|
xcvr->sprom[0]);
|
|
modinfo->type = 0;
|
|
modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ionic_get_module_eeprom(struct net_device *netdev,
|
|
struct ethtool_eeprom *ee,
|
|
u8 *data)
|
|
{
|
|
struct ionic_lif *lif = netdev_priv(netdev);
|
|
struct ionic_dev *idev = &lif->ionic->idev;
|
|
struct ionic_xcvr_status *xcvr;
|
|
char tbuf[sizeof(xcvr->sprom)];
|
|
int count = 10;
|
|
u32 len;
|
|
|
|
/* The NIC keeps the module prom up-to-date in the DMA space
|
|
* so we can simply copy the module bytes into the data buffer.
|
|
*/
|
|
xcvr = &idev->port_info->status.xcvr;
|
|
len = min_t(u32, sizeof(xcvr->sprom), ee->len);
|
|
|
|
do {
|
|
memcpy(data, xcvr->sprom, len);
|
|
memcpy(tbuf, xcvr->sprom, len);
|
|
|
|
/* Let's make sure we got a consistent copy */
|
|
if (!memcmp(data, tbuf, len))
|
|
break;
|
|
|
|
} while (--count);
|
|
|
|
if (!count)
|
|
return -ETIMEDOUT;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ionic_get_ts_info(struct net_device *netdev,
|
|
struct kernel_ethtool_ts_info *info)
|
|
{
|
|
struct ionic_lif *lif = netdev_priv(netdev);
|
|
struct ionic *ionic = lif->ionic;
|
|
__le64 mask;
|
|
|
|
if (!lif->phc || !lif->phc->ptp)
|
|
return ethtool_op_get_ts_info(netdev, info);
|
|
|
|
info->phc_index = ptp_clock_index(lif->phc->ptp);
|
|
|
|
info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
|
|
SOF_TIMESTAMPING_TX_HARDWARE |
|
|
SOF_TIMESTAMPING_RX_HARDWARE |
|
|
SOF_TIMESTAMPING_RAW_HARDWARE;
|
|
|
|
/* tx modes */
|
|
|
|
info->tx_types = BIT(HWTSTAMP_TX_OFF) |
|
|
BIT(HWTSTAMP_TX_ON);
|
|
|
|
mask = cpu_to_le64(BIT_ULL(IONIC_TXSTAMP_ONESTEP_SYNC));
|
|
if (ionic->ident.lif.eth.hwstamp_tx_modes & mask)
|
|
info->tx_types |= BIT(HWTSTAMP_TX_ONESTEP_SYNC);
|
|
|
|
mask = cpu_to_le64(BIT_ULL(IONIC_TXSTAMP_ONESTEP_P2P));
|
|
if (ionic->ident.lif.eth.hwstamp_tx_modes & mask)
|
|
info->tx_types |= BIT(HWTSTAMP_TX_ONESTEP_P2P);
|
|
|
|
/* rx filters */
|
|
|
|
info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
|
|
BIT(HWTSTAMP_FILTER_ALL);
|
|
|
|
mask = cpu_to_le64(IONIC_PKT_CLS_NTP_ALL);
|
|
if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask)
|
|
info->rx_filters |= BIT(HWTSTAMP_FILTER_NTP_ALL);
|
|
|
|
mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_SYNC);
|
|
if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask)
|
|
info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC);
|
|
|
|
mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_DREQ);
|
|
if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask)
|
|
info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ);
|
|
|
|
mask = cpu_to_le64(IONIC_PKT_CLS_PTP1_ALL);
|
|
if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask)
|
|
info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
|
|
|
|
mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_SYNC);
|
|
if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask)
|
|
info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC);
|
|
|
|
mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_DREQ);
|
|
if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask)
|
|
info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ);
|
|
|
|
mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L4_ALL);
|
|
if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask)
|
|
info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
|
|
|
|
mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_SYNC);
|
|
if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask)
|
|
info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC);
|
|
|
|
mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_DREQ);
|
|
if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask)
|
|
info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ);
|
|
|
|
mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_L2_ALL);
|
|
if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask)
|
|
info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT);
|
|
|
|
mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_SYNC);
|
|
if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask)
|
|
info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_SYNC);
|
|
|
|
mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_DREQ);
|
|
if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask)
|
|
info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
|
|
|
|
mask = cpu_to_le64(IONIC_PKT_CLS_PTP2_ALL);
|
|
if ((ionic->ident.lif.eth.hwstamp_rx_filters & mask) == mask)
|
|
info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ionic_nway_reset(struct net_device *netdev)
|
|
{
|
|
struct ionic_lif *lif = netdev_priv(netdev);
|
|
struct ionic *ionic = lif->ionic;
|
|
int err = 0;
|
|
|
|
if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
|
|
return -EBUSY;
|
|
|
|
/* flap the link to force auto-negotiation */
|
|
|
|
mutex_lock(&ionic->dev_cmd_lock);
|
|
|
|
ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_DOWN);
|
|
err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
|
|
|
|
if (!err) {
|
|
ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_UP);
|
|
err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
|
|
}
|
|
|
|
mutex_unlock(&ionic->dev_cmd_lock);
|
|
|
|
return err;
|
|
}
|
|
|
|
static const struct ethtool_ops ionic_ethtool_ops = {
|
|
.supported_coalesce_params = ETHTOOL_COALESCE_USECS |
|
|
ETHTOOL_COALESCE_USE_ADAPTIVE_RX |
|
|
ETHTOOL_COALESCE_USE_ADAPTIVE_TX,
|
|
.supported_ring_params = ETHTOOL_RING_USE_TX_PUSH |
|
|
ETHTOOL_RING_USE_RX_PUSH,
|
|
.get_drvinfo = ionic_get_drvinfo,
|
|
.get_regs_len = ionic_get_regs_len,
|
|
.get_regs = ionic_get_regs,
|
|
.get_link = ethtool_op_get_link,
|
|
.get_link_ext_stats = ionic_get_link_ext_stats,
|
|
.get_link_ksettings = ionic_get_link_ksettings,
|
|
.set_link_ksettings = ionic_set_link_ksettings,
|
|
.get_coalesce = ionic_get_coalesce,
|
|
.set_coalesce = ionic_set_coalesce,
|
|
.get_ringparam = ionic_get_ringparam,
|
|
.set_ringparam = ionic_set_ringparam,
|
|
.get_channels = ionic_get_channels,
|
|
.set_channels = ionic_set_channels,
|
|
.get_strings = ionic_get_strings,
|
|
.get_ethtool_stats = ionic_get_stats,
|
|
.get_sset_count = ionic_get_sset_count,
|
|
.get_rxnfc = ionic_get_rxnfc,
|
|
.get_rxfh_indir_size = ionic_get_rxfh_indir_size,
|
|
.get_rxfh_key_size = ionic_get_rxfh_key_size,
|
|
.get_rxfh = ionic_get_rxfh,
|
|
.set_rxfh = ionic_set_rxfh,
|
|
.get_tunable = ionic_get_tunable,
|
|
.set_tunable = ionic_set_tunable,
|
|
.get_module_info = ionic_get_module_info,
|
|
.get_module_eeprom = ionic_get_module_eeprom,
|
|
.get_pauseparam = ionic_get_pauseparam,
|
|
.set_pauseparam = ionic_set_pauseparam,
|
|
.get_fecparam = ionic_get_fecparam,
|
|
.set_fecparam = ionic_set_fecparam,
|
|
.get_ts_info = ionic_get_ts_info,
|
|
.nway_reset = ionic_nway_reset,
|
|
};
|
|
|
|
void ionic_ethtool_set_ops(struct net_device *netdev)
|
|
{
|
|
netdev->ethtool_ops = &ionic_ethtool_ops;
|
|
}
|