879 lines
		
	
	
		
			21 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			879 lines
		
	
	
		
			21 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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| /* Copyright (c) 2021, Microsoft Corporation. */
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| 
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| #include <net/mana/gdma.h>
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| #include <net/mana/hw_channel.h>
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| #include <linux/vmalloc.h>
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| 
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| static int mana_hwc_get_msg_index(struct hw_channel_context *hwc, u16 *msg_id)
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| {
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| 	struct gdma_resource *r = &hwc->inflight_msg_res;
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| 	unsigned long flags;
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| 	u32 index;
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| 
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| 	down(&hwc->sema);
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| 
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| 	spin_lock_irqsave(&r->lock, flags);
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| 
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| 	index = find_first_zero_bit(hwc->inflight_msg_res.map,
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| 				    hwc->inflight_msg_res.size);
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| 
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| 	bitmap_set(hwc->inflight_msg_res.map, index, 1);
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| 
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| 	spin_unlock_irqrestore(&r->lock, flags);
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| 
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| 	*msg_id = index;
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| 
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| 	return 0;
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| }
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| 
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| static void mana_hwc_put_msg_index(struct hw_channel_context *hwc, u16 msg_id)
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| {
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| 	struct gdma_resource *r = &hwc->inflight_msg_res;
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| 	unsigned long flags;
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| 
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| 	spin_lock_irqsave(&r->lock, flags);
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| 	bitmap_clear(hwc->inflight_msg_res.map, msg_id, 1);
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| 	spin_unlock_irqrestore(&r->lock, flags);
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| 
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| 	up(&hwc->sema);
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| }
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| 
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| static int mana_hwc_verify_resp_msg(const struct hwc_caller_ctx *caller_ctx,
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| 				    const struct gdma_resp_hdr *resp_msg,
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| 				    u32 resp_len)
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| {
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| 	if (resp_len < sizeof(*resp_msg))
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| 		return -EPROTO;
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| 
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| 	if (resp_len > caller_ctx->output_buflen)
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| 		return -EPROTO;
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| 
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| 	return 0;
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| }
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| 
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| static int mana_hwc_post_rx_wqe(const struct hwc_wq *hwc_rxq,
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| 				struct hwc_work_request *req)
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| {
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| 	struct device *dev = hwc_rxq->hwc->dev;
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| 	struct gdma_sge *sge;
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| 	int err;
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| 
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| 	sge = &req->sge;
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| 	sge->address = (u64)req->buf_sge_addr;
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| 	sge->mem_key = hwc_rxq->msg_buf->gpa_mkey;
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| 	sge->size = req->buf_len;
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| 
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| 	memset(&req->wqe_req, 0, sizeof(struct gdma_wqe_request));
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| 	req->wqe_req.sgl = sge;
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| 	req->wqe_req.num_sge = 1;
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| 	req->wqe_req.client_data_unit = 0;
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| 
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| 	err = mana_gd_post_and_ring(hwc_rxq->gdma_wq, &req->wqe_req, NULL);
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| 	if (err)
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| 		dev_err(dev, "Failed to post WQE on HWC RQ: %d\n", err);
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| 	return err;
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| }
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| 
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| static void mana_hwc_handle_resp(struct hw_channel_context *hwc, u32 resp_len,
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| 				 struct hwc_work_request *rx_req)
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| {
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| 	const struct gdma_resp_hdr *resp_msg = rx_req->buf_va;
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| 	struct hwc_caller_ctx *ctx;
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| 	int err;
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| 
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| 	if (!test_bit(resp_msg->response.hwc_msg_id,
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| 		      hwc->inflight_msg_res.map)) {
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| 		dev_err(hwc->dev, "hwc_rx: invalid msg_id = %u\n",
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| 			resp_msg->response.hwc_msg_id);
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| 		mana_hwc_post_rx_wqe(hwc->rxq, rx_req);
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| 		return;
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| 	}
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| 
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| 	ctx = hwc->caller_ctx + resp_msg->response.hwc_msg_id;
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| 	err = mana_hwc_verify_resp_msg(ctx, resp_msg, resp_len);
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| 	if (err)
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| 		goto out;
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| 
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| 	ctx->status_code = resp_msg->status;
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| 
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| 	memcpy(ctx->output_buf, resp_msg, resp_len);
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| out:
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| 	ctx->error = err;
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| 
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| 	/* Must post rx wqe before complete(), otherwise the next rx may
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| 	 * hit no_wqe error.
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| 	 */
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| 	mana_hwc_post_rx_wqe(hwc->rxq, rx_req);
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| 
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| 	complete(&ctx->comp_event);
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| }
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| 
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| static void mana_hwc_init_event_handler(void *ctx, struct gdma_queue *q_self,
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| 					struct gdma_event *event)
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| {
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| 	struct hw_channel_context *hwc = ctx;
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| 	struct gdma_dev *gd = hwc->gdma_dev;
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| 	union hwc_init_type_data type_data;
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| 	union hwc_init_eq_id_db eq_db;
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| 	u32 type, val;
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| 
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| 	switch (event->type) {
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| 	case GDMA_EQE_HWC_INIT_EQ_ID_DB:
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| 		eq_db.as_uint32 = event->details[0];
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| 		hwc->cq->gdma_eq->id = eq_db.eq_id;
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| 		gd->doorbell = eq_db.doorbell;
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| 		break;
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| 
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| 	case GDMA_EQE_HWC_INIT_DATA:
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| 		type_data.as_uint32 = event->details[0];
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| 		type = type_data.type;
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| 		val = type_data.value;
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| 
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| 		switch (type) {
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| 		case HWC_INIT_DATA_CQID:
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| 			hwc->cq->gdma_cq->id = val;
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| 			break;
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| 
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| 		case HWC_INIT_DATA_RQID:
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| 			hwc->rxq->gdma_wq->id = val;
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| 			break;
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| 
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| 		case HWC_INIT_DATA_SQID:
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| 			hwc->txq->gdma_wq->id = val;
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| 			break;
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| 
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| 		case HWC_INIT_DATA_QUEUE_DEPTH:
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| 			hwc->hwc_init_q_depth_max = (u16)val;
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| 			break;
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| 
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| 		case HWC_INIT_DATA_MAX_REQUEST:
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| 			hwc->hwc_init_max_req_msg_size = val;
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| 			break;
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| 
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| 		case HWC_INIT_DATA_MAX_RESPONSE:
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| 			hwc->hwc_init_max_resp_msg_size = val;
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| 			break;
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| 
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| 		case HWC_INIT_DATA_MAX_NUM_CQS:
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| 			gd->gdma_context->max_num_cqs = val;
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| 			break;
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| 
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| 		case HWC_INIT_DATA_PDID:
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| 			hwc->gdma_dev->pdid = val;
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| 			break;
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| 
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| 		case HWC_INIT_DATA_GPA_MKEY:
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| 			hwc->rxq->msg_buf->gpa_mkey = val;
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| 			hwc->txq->msg_buf->gpa_mkey = val;
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| 			break;
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| 
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| 		case HWC_INIT_DATA_PF_DEST_RQ_ID:
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| 			hwc->pf_dest_vrq_id = val;
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| 			break;
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| 
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| 		case HWC_INIT_DATA_PF_DEST_CQ_ID:
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| 			hwc->pf_dest_vrcq_id = val;
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| 			break;
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| 		}
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| 
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| 		break;
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| 
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| 	case GDMA_EQE_HWC_INIT_DONE:
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| 		complete(&hwc->hwc_init_eqe_comp);
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| 		break;
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| 
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| 	case GDMA_EQE_HWC_SOC_RECONFIG_DATA:
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| 		type_data.as_uint32 = event->details[0];
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| 		type = type_data.type;
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| 		val = type_data.value;
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| 
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| 		switch (type) {
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| 		case HWC_DATA_CFG_HWC_TIMEOUT:
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| 			hwc->hwc_timeout = val;
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| 			break;
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| 
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| 		default:
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| 			dev_warn(hwc->dev, "Received unknown reconfig type %u\n", type);
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| 			break;
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| 		}
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| 
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| 		break;
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| 
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| 	default:
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| 		dev_warn(hwc->dev, "Received unknown gdma event %u\n", event->type);
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| 		/* Ignore unknown events, which should never happen. */
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| 		break;
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| 	}
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| }
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| 
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| static void mana_hwc_rx_event_handler(void *ctx, u32 gdma_rxq_id,
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| 				      const struct hwc_rx_oob *rx_oob)
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| {
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| 	struct hw_channel_context *hwc = ctx;
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| 	struct hwc_wq *hwc_rxq = hwc->rxq;
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| 	struct hwc_work_request *rx_req;
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| 	struct gdma_resp_hdr *resp;
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| 	struct gdma_wqe *dma_oob;
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| 	struct gdma_queue *rq;
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| 	struct gdma_sge *sge;
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| 	u64 rq_base_addr;
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| 	u64 rx_req_idx;
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| 	u8 *wqe;
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| 
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| 	if (WARN_ON_ONCE(hwc_rxq->gdma_wq->id != gdma_rxq_id))
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| 		return;
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| 
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| 	rq = hwc_rxq->gdma_wq;
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| 	wqe = mana_gd_get_wqe_ptr(rq, rx_oob->wqe_offset / GDMA_WQE_BU_SIZE);
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| 	dma_oob = (struct gdma_wqe *)wqe;
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| 
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| 	sge = (struct gdma_sge *)(wqe + 8 + dma_oob->inline_oob_size_div4 * 4);
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| 
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| 	/* Select the RX work request for virtual address and for reposting. */
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| 	rq_base_addr = hwc_rxq->msg_buf->mem_info.dma_handle;
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| 	rx_req_idx = (sge->address - rq_base_addr) / hwc->max_req_msg_size;
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| 
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| 	rx_req = &hwc_rxq->msg_buf->reqs[rx_req_idx];
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| 	resp = (struct gdma_resp_hdr *)rx_req->buf_va;
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| 
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| 	if (resp->response.hwc_msg_id >= hwc->num_inflight_msg) {
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| 		dev_err(hwc->dev, "HWC RX: wrong msg_id=%u\n",
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| 			resp->response.hwc_msg_id);
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| 		return;
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| 	}
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| 
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| 	mana_hwc_handle_resp(hwc, rx_oob->tx_oob_data_size, rx_req);
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| 
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| 	/* Can no longer use 'resp', because the buffer is posted to the HW
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| 	 * in mana_hwc_handle_resp() above.
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| 	 */
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| 	resp = NULL;
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| }
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| 
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| static void mana_hwc_tx_event_handler(void *ctx, u32 gdma_txq_id,
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| 				      const struct hwc_rx_oob *rx_oob)
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| {
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| 	struct hw_channel_context *hwc = ctx;
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| 	struct hwc_wq *hwc_txq = hwc->txq;
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| 
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| 	WARN_ON_ONCE(!hwc_txq || hwc_txq->gdma_wq->id != gdma_txq_id);
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| }
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| 
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| static int mana_hwc_create_gdma_wq(struct hw_channel_context *hwc,
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| 				   enum gdma_queue_type type, u64 queue_size,
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| 				   struct gdma_queue **queue)
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| {
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| 	struct gdma_queue_spec spec = {};
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| 
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| 	if (type != GDMA_SQ && type != GDMA_RQ)
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| 		return -EINVAL;
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| 
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| 	spec.type = type;
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| 	spec.monitor_avl_buf = false;
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| 	spec.queue_size = queue_size;
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| 
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| 	return mana_gd_create_hwc_queue(hwc->gdma_dev, &spec, queue);
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| }
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| 
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| static int mana_hwc_create_gdma_cq(struct hw_channel_context *hwc,
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| 				   u64 queue_size,
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| 				   void *ctx, gdma_cq_callback *cb,
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| 				   struct gdma_queue *parent_eq,
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| 				   struct gdma_queue **queue)
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| {
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| 	struct gdma_queue_spec spec = {};
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| 
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| 	spec.type = GDMA_CQ;
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| 	spec.monitor_avl_buf = false;
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| 	spec.queue_size = queue_size;
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| 	spec.cq.context = ctx;
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| 	spec.cq.callback = cb;
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| 	spec.cq.parent_eq = parent_eq;
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| 
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| 	return mana_gd_create_hwc_queue(hwc->gdma_dev, &spec, queue);
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| }
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| 
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| static int mana_hwc_create_gdma_eq(struct hw_channel_context *hwc,
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| 				   u64 queue_size,
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| 				   void *ctx, gdma_eq_callback *cb,
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| 				   struct gdma_queue **queue)
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| {
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| 	struct gdma_queue_spec spec = {};
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| 
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| 	spec.type = GDMA_EQ;
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| 	spec.monitor_avl_buf = false;
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| 	spec.queue_size = queue_size;
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| 	spec.eq.context = ctx;
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| 	spec.eq.callback = cb;
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| 	spec.eq.log2_throttle_limit = DEFAULT_LOG2_THROTTLING_FOR_ERROR_EQ;
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| 	spec.eq.msix_index = 0;
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| 
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| 	return mana_gd_create_hwc_queue(hwc->gdma_dev, &spec, queue);
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| }
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| 
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| static void mana_hwc_comp_event(void *ctx, struct gdma_queue *q_self)
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| {
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| 	struct hwc_rx_oob comp_data = {};
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| 	struct gdma_comp *completions;
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| 	struct hwc_cq *hwc_cq = ctx;
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| 	int comp_read, i;
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| 
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| 	WARN_ON_ONCE(hwc_cq->gdma_cq != q_self);
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| 
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| 	completions = hwc_cq->comp_buf;
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| 	comp_read = mana_gd_poll_cq(q_self, completions, hwc_cq->queue_depth);
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| 	WARN_ON_ONCE(comp_read <= 0 || comp_read > hwc_cq->queue_depth);
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| 
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| 	for (i = 0; i < comp_read; ++i) {
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| 		comp_data = *(struct hwc_rx_oob *)completions[i].cqe_data;
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| 
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| 		if (completions[i].is_sq)
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| 			hwc_cq->tx_event_handler(hwc_cq->tx_event_ctx,
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| 						completions[i].wq_num,
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| 						&comp_data);
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| 		else
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| 			hwc_cq->rx_event_handler(hwc_cq->rx_event_ctx,
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| 						completions[i].wq_num,
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| 						&comp_data);
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| 	}
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| 
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| 	mana_gd_ring_cq(q_self, SET_ARM_BIT);
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| }
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| 
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| static void mana_hwc_destroy_cq(struct gdma_context *gc, struct hwc_cq *hwc_cq)
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| {
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| 	kfree(hwc_cq->comp_buf);
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| 
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| 	if (hwc_cq->gdma_cq)
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| 		mana_gd_destroy_queue(gc, hwc_cq->gdma_cq);
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| 
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| 	if (hwc_cq->gdma_eq)
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| 		mana_gd_destroy_queue(gc, hwc_cq->gdma_eq);
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| 
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| 	kfree(hwc_cq);
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| }
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| 
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| static int mana_hwc_create_cq(struct hw_channel_context *hwc, u16 q_depth,
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| 			      gdma_eq_callback *callback, void *ctx,
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| 			      hwc_rx_event_handler_t *rx_ev_hdlr,
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| 			      void *rx_ev_ctx,
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| 			      hwc_tx_event_handler_t *tx_ev_hdlr,
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| 			      void *tx_ev_ctx, struct hwc_cq **hwc_cq_ptr)
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| {
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| 	struct gdma_queue *eq, *cq;
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| 	struct gdma_comp *comp_buf;
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| 	struct hwc_cq *hwc_cq;
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| 	u32 eq_size, cq_size;
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| 	int err;
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| 
 | |
| 	eq_size = roundup_pow_of_two(GDMA_EQE_SIZE * q_depth);
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| 	if (eq_size < MANA_MIN_QSIZE)
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| 		eq_size = MANA_MIN_QSIZE;
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| 
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| 	cq_size = roundup_pow_of_two(GDMA_CQE_SIZE * q_depth);
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| 	if (cq_size < MANA_MIN_QSIZE)
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| 		cq_size = MANA_MIN_QSIZE;
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| 
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| 	hwc_cq = kzalloc(sizeof(*hwc_cq), GFP_KERNEL);
 | |
| 	if (!hwc_cq)
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| 		return -ENOMEM;
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| 
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| 	err = mana_hwc_create_gdma_eq(hwc, eq_size, ctx, callback, &eq);
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| 	if (err) {
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| 		dev_err(hwc->dev, "Failed to create HWC EQ for RQ: %d\n", err);
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| 		goto out;
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| 	}
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| 	hwc_cq->gdma_eq = eq;
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| 
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| 	err = mana_hwc_create_gdma_cq(hwc, cq_size, hwc_cq, mana_hwc_comp_event,
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| 				      eq, &cq);
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| 	if (err) {
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| 		dev_err(hwc->dev, "Failed to create HWC CQ for RQ: %d\n", err);
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| 		goto out;
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| 	}
 | |
| 	hwc_cq->gdma_cq = cq;
 | |
| 
 | |
| 	comp_buf = kcalloc(q_depth, sizeof(*comp_buf), GFP_KERNEL);
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| 	if (!comp_buf) {
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| 		err = -ENOMEM;
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| 		goto out;
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| 	}
 | |
| 
 | |
| 	hwc_cq->hwc = hwc;
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| 	hwc_cq->comp_buf = comp_buf;
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| 	hwc_cq->queue_depth = q_depth;
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| 	hwc_cq->rx_event_handler = rx_ev_hdlr;
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| 	hwc_cq->rx_event_ctx = rx_ev_ctx;
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| 	hwc_cq->tx_event_handler = tx_ev_hdlr;
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| 	hwc_cq->tx_event_ctx = tx_ev_ctx;
 | |
| 
 | |
| 	*hwc_cq_ptr = hwc_cq;
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| 	return 0;
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| out:
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| 	mana_hwc_destroy_cq(hwc->gdma_dev->gdma_context, hwc_cq);
 | |
| 	return err;
 | |
| }
 | |
| 
 | |
| static int mana_hwc_alloc_dma_buf(struct hw_channel_context *hwc, u16 q_depth,
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| 				  u32 max_msg_size,
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| 				  struct hwc_dma_buf **dma_buf_ptr)
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| {
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| 	struct gdma_context *gc = hwc->gdma_dev->gdma_context;
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| 	struct hwc_work_request *hwc_wr;
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| 	struct hwc_dma_buf *dma_buf;
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| 	struct gdma_mem_info *gmi;
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| 	void *virt_addr;
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| 	u32 buf_size;
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| 	u8 *base_pa;
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| 	int err;
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| 	u16 i;
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| 
 | |
| 	dma_buf = kzalloc(struct_size(dma_buf, reqs, q_depth), GFP_KERNEL);
 | |
| 	if (!dma_buf)
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| 		return -ENOMEM;
 | |
| 
 | |
| 	dma_buf->num_reqs = q_depth;
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| 
 | |
| 	buf_size = MANA_PAGE_ALIGN(q_depth * max_msg_size);
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| 
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| 	gmi = &dma_buf->mem_info;
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| 	err = mana_gd_alloc_memory(gc, buf_size, gmi);
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| 	if (err) {
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| 		dev_err(hwc->dev, "Failed to allocate DMA buffer: %d\n", err);
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| 		goto out;
 | |
| 	}
 | |
| 
 | |
| 	virt_addr = dma_buf->mem_info.virt_addr;
 | |
| 	base_pa = (u8 *)dma_buf->mem_info.dma_handle;
 | |
| 
 | |
| 	for (i = 0; i < q_depth; i++) {
 | |
| 		hwc_wr = &dma_buf->reqs[i];
 | |
| 
 | |
| 		hwc_wr->buf_va = virt_addr + i * max_msg_size;
 | |
| 		hwc_wr->buf_sge_addr = base_pa + i * max_msg_size;
 | |
| 
 | |
| 		hwc_wr->buf_len = max_msg_size;
 | |
| 	}
 | |
| 
 | |
| 	*dma_buf_ptr = dma_buf;
 | |
| 	return 0;
 | |
| out:
 | |
| 	kfree(dma_buf);
 | |
| 	return err;
 | |
| }
 | |
| 
 | |
| static void mana_hwc_dealloc_dma_buf(struct hw_channel_context *hwc,
 | |
| 				     struct hwc_dma_buf *dma_buf)
 | |
| {
 | |
| 	if (!dma_buf)
 | |
| 		return;
 | |
| 
 | |
| 	mana_gd_free_memory(&dma_buf->mem_info);
 | |
| 
 | |
| 	kfree(dma_buf);
 | |
| }
 | |
| 
 | |
| static void mana_hwc_destroy_wq(struct hw_channel_context *hwc,
 | |
| 				struct hwc_wq *hwc_wq)
 | |
| {
 | |
| 	mana_hwc_dealloc_dma_buf(hwc, hwc_wq->msg_buf);
 | |
| 
 | |
| 	if (hwc_wq->gdma_wq)
 | |
| 		mana_gd_destroy_queue(hwc->gdma_dev->gdma_context,
 | |
| 				      hwc_wq->gdma_wq);
 | |
| 
 | |
| 	kfree(hwc_wq);
 | |
| }
 | |
| 
 | |
| static int mana_hwc_create_wq(struct hw_channel_context *hwc,
 | |
| 			      enum gdma_queue_type q_type, u16 q_depth,
 | |
| 			      u32 max_msg_size, struct hwc_cq *hwc_cq,
 | |
| 			      struct hwc_wq **hwc_wq_ptr)
 | |
| {
 | |
| 	struct gdma_queue *queue;
 | |
| 	struct hwc_wq *hwc_wq;
 | |
| 	u32 queue_size;
 | |
| 	int err;
 | |
| 
 | |
| 	WARN_ON(q_type != GDMA_SQ && q_type != GDMA_RQ);
 | |
| 
 | |
| 	if (q_type == GDMA_RQ)
 | |
| 		queue_size = roundup_pow_of_two(GDMA_MAX_RQE_SIZE * q_depth);
 | |
| 	else
 | |
| 		queue_size = roundup_pow_of_two(GDMA_MAX_SQE_SIZE * q_depth);
 | |
| 
 | |
| 	if (queue_size < MANA_MIN_QSIZE)
 | |
| 		queue_size = MANA_MIN_QSIZE;
 | |
| 
 | |
| 	hwc_wq = kzalloc(sizeof(*hwc_wq), GFP_KERNEL);
 | |
| 	if (!hwc_wq)
 | |
| 		return -ENOMEM;
 | |
| 
 | |
| 	err = mana_hwc_create_gdma_wq(hwc, q_type, queue_size, &queue);
 | |
| 	if (err)
 | |
| 		goto out;
 | |
| 
 | |
| 	hwc_wq->hwc = hwc;
 | |
| 	hwc_wq->gdma_wq = queue;
 | |
| 	hwc_wq->queue_depth = q_depth;
 | |
| 	hwc_wq->hwc_cq = hwc_cq;
 | |
| 
 | |
| 	err = mana_hwc_alloc_dma_buf(hwc, q_depth, max_msg_size,
 | |
| 				     &hwc_wq->msg_buf);
 | |
| 	if (err)
 | |
| 		goto out;
 | |
| 
 | |
| 	*hwc_wq_ptr = hwc_wq;
 | |
| 	return 0;
 | |
| out:
 | |
| 	if (err)
 | |
| 		mana_hwc_destroy_wq(hwc, hwc_wq);
 | |
| 	return err;
 | |
| }
 | |
| 
 | |
| static int mana_hwc_post_tx_wqe(const struct hwc_wq *hwc_txq,
 | |
| 				struct hwc_work_request *req,
 | |
| 				u32 dest_virt_rq_id, u32 dest_virt_rcq_id,
 | |
| 				bool dest_pf)
 | |
| {
 | |
| 	struct device *dev = hwc_txq->hwc->dev;
 | |
| 	struct hwc_tx_oob *tx_oob;
 | |
| 	struct gdma_sge *sge;
 | |
| 	int err;
 | |
| 
 | |
| 	if (req->msg_size == 0 || req->msg_size > req->buf_len) {
 | |
| 		dev_err(dev, "wrong msg_size: %u, buf_len: %u\n",
 | |
| 			req->msg_size, req->buf_len);
 | |
| 		return -EINVAL;
 | |
| 	}
 | |
| 
 | |
| 	tx_oob = &req->tx_oob;
 | |
| 
 | |
| 	tx_oob->vrq_id = dest_virt_rq_id;
 | |
| 	tx_oob->dest_vfid = 0;
 | |
| 	tx_oob->vrcq_id = dest_virt_rcq_id;
 | |
| 	tx_oob->vscq_id = hwc_txq->hwc_cq->gdma_cq->id;
 | |
| 	tx_oob->loopback = false;
 | |
| 	tx_oob->lso_override = false;
 | |
| 	tx_oob->dest_pf = dest_pf;
 | |
| 	tx_oob->vsq_id = hwc_txq->gdma_wq->id;
 | |
| 
 | |
| 	sge = &req->sge;
 | |
| 	sge->address = (u64)req->buf_sge_addr;
 | |
| 	sge->mem_key = hwc_txq->msg_buf->gpa_mkey;
 | |
| 	sge->size = req->msg_size;
 | |
| 
 | |
| 	memset(&req->wqe_req, 0, sizeof(struct gdma_wqe_request));
 | |
| 	req->wqe_req.sgl = sge;
 | |
| 	req->wqe_req.num_sge = 1;
 | |
| 	req->wqe_req.inline_oob_size = sizeof(struct hwc_tx_oob);
 | |
| 	req->wqe_req.inline_oob_data = tx_oob;
 | |
| 	req->wqe_req.client_data_unit = 0;
 | |
| 
 | |
| 	err = mana_gd_post_and_ring(hwc_txq->gdma_wq, &req->wqe_req, NULL);
 | |
| 	if (err)
 | |
| 		dev_err(dev, "Failed to post WQE on HWC SQ: %d\n", err);
 | |
| 	return err;
 | |
| }
 | |
| 
 | |
| static int mana_hwc_init_inflight_msg(struct hw_channel_context *hwc,
 | |
| 				      u16 num_msg)
 | |
| {
 | |
| 	int err;
 | |
| 
 | |
| 	sema_init(&hwc->sema, num_msg);
 | |
| 
 | |
| 	err = mana_gd_alloc_res_map(num_msg, &hwc->inflight_msg_res);
 | |
| 	if (err)
 | |
| 		dev_err(hwc->dev, "Failed to init inflight_msg_res: %d\n", err);
 | |
| 	return err;
 | |
| }
 | |
| 
 | |
| static int mana_hwc_test_channel(struct hw_channel_context *hwc, u16 q_depth,
 | |
| 				 u32 max_req_msg_size, u32 max_resp_msg_size)
 | |
| {
 | |
| 	struct gdma_context *gc = hwc->gdma_dev->gdma_context;
 | |
| 	struct hwc_wq *hwc_rxq = hwc->rxq;
 | |
| 	struct hwc_work_request *req;
 | |
| 	struct hwc_caller_ctx *ctx;
 | |
| 	int err;
 | |
| 	int i;
 | |
| 
 | |
| 	/* Post all WQEs on the RQ */
 | |
| 	for (i = 0; i < q_depth; i++) {
 | |
| 		req = &hwc_rxq->msg_buf->reqs[i];
 | |
| 		err = mana_hwc_post_rx_wqe(hwc_rxq, req);
 | |
| 		if (err)
 | |
| 			return err;
 | |
| 	}
 | |
| 
 | |
| 	ctx = kcalloc(q_depth, sizeof(*ctx), GFP_KERNEL);
 | |
| 	if (!ctx)
 | |
| 		return -ENOMEM;
 | |
| 
 | |
| 	for (i = 0; i < q_depth; ++i)
 | |
| 		init_completion(&ctx[i].comp_event);
 | |
| 
 | |
| 	hwc->caller_ctx = ctx;
 | |
| 
 | |
| 	return mana_gd_test_eq(gc, hwc->cq->gdma_eq);
 | |
| }
 | |
| 
 | |
| static int mana_hwc_establish_channel(struct gdma_context *gc, u16 *q_depth,
 | |
| 				      u32 *max_req_msg_size,
 | |
| 				      u32 *max_resp_msg_size)
 | |
| {
 | |
| 	struct hw_channel_context *hwc = gc->hwc.driver_data;
 | |
| 	struct gdma_queue *rq = hwc->rxq->gdma_wq;
 | |
| 	struct gdma_queue *sq = hwc->txq->gdma_wq;
 | |
| 	struct gdma_queue *eq = hwc->cq->gdma_eq;
 | |
| 	struct gdma_queue *cq = hwc->cq->gdma_cq;
 | |
| 	int err;
 | |
| 
 | |
| 	init_completion(&hwc->hwc_init_eqe_comp);
 | |
| 
 | |
| 	err = mana_smc_setup_hwc(&gc->shm_channel, false,
 | |
| 				 eq->mem_info.dma_handle,
 | |
| 				 cq->mem_info.dma_handle,
 | |
| 				 rq->mem_info.dma_handle,
 | |
| 				 sq->mem_info.dma_handle,
 | |
| 				 eq->eq.msix_index);
 | |
| 	if (err)
 | |
| 		return err;
 | |
| 
 | |
| 	if (!wait_for_completion_timeout(&hwc->hwc_init_eqe_comp, 60 * HZ))
 | |
| 		return -ETIMEDOUT;
 | |
| 
 | |
| 	*q_depth = hwc->hwc_init_q_depth_max;
 | |
| 	*max_req_msg_size = hwc->hwc_init_max_req_msg_size;
 | |
| 	*max_resp_msg_size = hwc->hwc_init_max_resp_msg_size;
 | |
| 
 | |
| 	/* Both were set in mana_hwc_init_event_handler(). */
 | |
| 	if (WARN_ON(cq->id >= gc->max_num_cqs))
 | |
| 		return -EPROTO;
 | |
| 
 | |
| 	gc->cq_table = vcalloc(gc->max_num_cqs, sizeof(struct gdma_queue *));
 | |
| 	if (!gc->cq_table)
 | |
| 		return -ENOMEM;
 | |
| 
 | |
| 	gc->cq_table[cq->id] = cq;
 | |
| 
 | |
| 	return 0;
 | |
| }
 | |
| 
 | |
| static int mana_hwc_init_queues(struct hw_channel_context *hwc, u16 q_depth,
 | |
| 				u32 max_req_msg_size, u32 max_resp_msg_size)
 | |
| {
 | |
| 	int err;
 | |
| 
 | |
| 	err = mana_hwc_init_inflight_msg(hwc, q_depth);
 | |
| 	if (err)
 | |
| 		return err;
 | |
| 
 | |
| 	/* CQ is shared by SQ and RQ, so CQ's queue depth is the sum of SQ
 | |
| 	 * queue depth and RQ queue depth.
 | |
| 	 */
 | |
| 	err = mana_hwc_create_cq(hwc, q_depth * 2,
 | |
| 				 mana_hwc_init_event_handler, hwc,
 | |
| 				 mana_hwc_rx_event_handler, hwc,
 | |
| 				 mana_hwc_tx_event_handler, hwc, &hwc->cq);
 | |
| 	if (err) {
 | |
| 		dev_err(hwc->dev, "Failed to create HWC CQ: %d\n", err);
 | |
| 		goto out;
 | |
| 	}
 | |
| 
 | |
| 	err = mana_hwc_create_wq(hwc, GDMA_RQ, q_depth, max_req_msg_size,
 | |
| 				 hwc->cq, &hwc->rxq);
 | |
| 	if (err) {
 | |
| 		dev_err(hwc->dev, "Failed to create HWC RQ: %d\n", err);
 | |
| 		goto out;
 | |
| 	}
 | |
| 
 | |
| 	err = mana_hwc_create_wq(hwc, GDMA_SQ, q_depth, max_resp_msg_size,
 | |
| 				 hwc->cq, &hwc->txq);
 | |
| 	if (err) {
 | |
| 		dev_err(hwc->dev, "Failed to create HWC SQ: %d\n", err);
 | |
| 		goto out;
 | |
| 	}
 | |
| 
 | |
| 	hwc->num_inflight_msg = q_depth;
 | |
| 	hwc->max_req_msg_size = max_req_msg_size;
 | |
| 
 | |
| 	return 0;
 | |
| out:
 | |
| 	/* mana_hwc_create_channel() will do the cleanup.*/
 | |
| 	return err;
 | |
| }
 | |
| 
 | |
| int mana_hwc_create_channel(struct gdma_context *gc)
 | |
| {
 | |
| 	u32 max_req_msg_size, max_resp_msg_size;
 | |
| 	struct gdma_dev *gd = &gc->hwc;
 | |
| 	struct hw_channel_context *hwc;
 | |
| 	u16 q_depth_max;
 | |
| 	int err;
 | |
| 
 | |
| 	hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
 | |
| 	if (!hwc)
 | |
| 		return -ENOMEM;
 | |
| 
 | |
| 	gd->gdma_context = gc;
 | |
| 	gd->driver_data = hwc;
 | |
| 	hwc->gdma_dev = gd;
 | |
| 	hwc->dev = gc->dev;
 | |
| 	hwc->hwc_timeout = HW_CHANNEL_WAIT_RESOURCE_TIMEOUT_MS;
 | |
| 
 | |
| 	/* HWC's instance number is always 0. */
 | |
| 	gd->dev_id.as_uint32 = 0;
 | |
| 	gd->dev_id.type = GDMA_DEVICE_HWC;
 | |
| 
 | |
| 	gd->pdid = INVALID_PDID;
 | |
| 	gd->doorbell = INVALID_DOORBELL;
 | |
| 
 | |
| 	/* mana_hwc_init_queues() only creates the required data structures,
 | |
| 	 * and doesn't touch the HWC device.
 | |
| 	 */
 | |
| 	err = mana_hwc_init_queues(hwc, HW_CHANNEL_VF_BOOTSTRAP_QUEUE_DEPTH,
 | |
| 				   HW_CHANNEL_MAX_REQUEST_SIZE,
 | |
| 				   HW_CHANNEL_MAX_RESPONSE_SIZE);
 | |
| 	if (err) {
 | |
| 		dev_err(hwc->dev, "Failed to initialize HWC: %d\n", err);
 | |
| 		goto out;
 | |
| 	}
 | |
| 
 | |
| 	err = mana_hwc_establish_channel(gc, &q_depth_max, &max_req_msg_size,
 | |
| 					 &max_resp_msg_size);
 | |
| 	if (err) {
 | |
| 		dev_err(hwc->dev, "Failed to establish HWC: %d\n", err);
 | |
| 		goto out;
 | |
| 	}
 | |
| 
 | |
| 	err = mana_hwc_test_channel(gc->hwc.driver_data,
 | |
| 				    HW_CHANNEL_VF_BOOTSTRAP_QUEUE_DEPTH,
 | |
| 				    max_req_msg_size, max_resp_msg_size);
 | |
| 	if (err) {
 | |
| 		dev_err(hwc->dev, "Failed to test HWC: %d\n", err);
 | |
| 		goto out;
 | |
| 	}
 | |
| 
 | |
| 	return 0;
 | |
| out:
 | |
| 	mana_hwc_destroy_channel(gc);
 | |
| 	return err;
 | |
| }
 | |
| 
 | |
| void mana_hwc_destroy_channel(struct gdma_context *gc)
 | |
| {
 | |
| 	struct hw_channel_context *hwc = gc->hwc.driver_data;
 | |
| 
 | |
| 	if (!hwc)
 | |
| 		return;
 | |
| 
 | |
| 	/* gc->max_num_cqs is set in mana_hwc_init_event_handler(). If it's
 | |
| 	 * non-zero, the HWC worked and we should tear down the HWC here.
 | |
| 	 */
 | |
| 	if (gc->max_num_cqs > 0) {
 | |
| 		mana_smc_teardown_hwc(&gc->shm_channel, false);
 | |
| 		gc->max_num_cqs = 0;
 | |
| 	}
 | |
| 
 | |
| 	kfree(hwc->caller_ctx);
 | |
| 	hwc->caller_ctx = NULL;
 | |
| 
 | |
| 	if (hwc->txq)
 | |
| 		mana_hwc_destroy_wq(hwc, hwc->txq);
 | |
| 
 | |
| 	if (hwc->rxq)
 | |
| 		mana_hwc_destroy_wq(hwc, hwc->rxq);
 | |
| 
 | |
| 	if (hwc->cq)
 | |
| 		mana_hwc_destroy_cq(hwc->gdma_dev->gdma_context, hwc->cq);
 | |
| 
 | |
| 	mana_gd_free_res_map(&hwc->inflight_msg_res);
 | |
| 
 | |
| 	hwc->num_inflight_msg = 0;
 | |
| 
 | |
| 	hwc->gdma_dev->doorbell = INVALID_DOORBELL;
 | |
| 	hwc->gdma_dev->pdid = INVALID_PDID;
 | |
| 
 | |
| 	hwc->hwc_timeout = 0;
 | |
| 
 | |
| 	kfree(hwc);
 | |
| 	gc->hwc.driver_data = NULL;
 | |
| 	gc->hwc.gdma_context = NULL;
 | |
| 
 | |
| 	vfree(gc->cq_table);
 | |
| 	gc->cq_table = NULL;
 | |
| }
 | |
| 
 | |
| int mana_hwc_send_request(struct hw_channel_context *hwc, u32 req_len,
 | |
| 			  const void *req, u32 resp_len, void *resp)
 | |
| {
 | |
| 	struct gdma_context *gc = hwc->gdma_dev->gdma_context;
 | |
| 	struct hwc_work_request *tx_wr;
 | |
| 	struct hwc_wq *txq = hwc->txq;
 | |
| 	struct gdma_req_hdr *req_msg;
 | |
| 	struct hwc_caller_ctx *ctx;
 | |
| 	u32 dest_vrcq = 0;
 | |
| 	u32 dest_vrq = 0;
 | |
| 	u16 msg_id;
 | |
| 	int err;
 | |
| 
 | |
| 	mana_hwc_get_msg_index(hwc, &msg_id);
 | |
| 
 | |
| 	tx_wr = &txq->msg_buf->reqs[msg_id];
 | |
| 
 | |
| 	if (req_len > tx_wr->buf_len) {
 | |
| 		dev_err(hwc->dev, "HWC: req msg size: %d > %d\n", req_len,
 | |
| 			tx_wr->buf_len);
 | |
| 		err = -EINVAL;
 | |
| 		goto out;
 | |
| 	}
 | |
| 
 | |
| 	ctx = hwc->caller_ctx + msg_id;
 | |
| 	ctx->output_buf = resp;
 | |
| 	ctx->output_buflen = resp_len;
 | |
| 
 | |
| 	req_msg = (struct gdma_req_hdr *)tx_wr->buf_va;
 | |
| 	if (req)
 | |
| 		memcpy(req_msg, req, req_len);
 | |
| 
 | |
| 	req_msg->req.hwc_msg_id = msg_id;
 | |
| 
 | |
| 	tx_wr->msg_size = req_len;
 | |
| 
 | |
| 	if (gc->is_pf) {
 | |
| 		dest_vrq = hwc->pf_dest_vrq_id;
 | |
| 		dest_vrcq = hwc->pf_dest_vrcq_id;
 | |
| 	}
 | |
| 
 | |
| 	err = mana_hwc_post_tx_wqe(txq, tx_wr, dest_vrq, dest_vrcq, false);
 | |
| 	if (err) {
 | |
| 		dev_err(hwc->dev, "HWC: Failed to post send WQE: %d\n", err);
 | |
| 		goto out;
 | |
| 	}
 | |
| 
 | |
| 	if (!wait_for_completion_timeout(&ctx->comp_event,
 | |
| 					 (msecs_to_jiffies(hwc->hwc_timeout)))) {
 | |
| 		dev_err(hwc->dev, "HWC: Request timed out!\n");
 | |
| 		err = -ETIMEDOUT;
 | |
| 		goto out;
 | |
| 	}
 | |
| 
 | |
| 	if (ctx->error) {
 | |
| 		err = ctx->error;
 | |
| 		goto out;
 | |
| 	}
 | |
| 
 | |
| 	if (ctx->status_code && ctx->status_code != GDMA_STATUS_MORE_ENTRIES) {
 | |
| 		dev_err(hwc->dev, "HWC: Failed hw_channel req: 0x%x\n",
 | |
| 			ctx->status_code);
 | |
| 		err = -EPROTO;
 | |
| 		goto out;
 | |
| 	}
 | |
| out:
 | |
| 	mana_hwc_put_msg_index(hwc, msg_id);
 | |
| 	return err;
 | |
| }
 |