108 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			108 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* SPDX-License-Identifier: GPL-2.0-or-later */
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| /*
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|  * Applied Micro X-Gene SoC Ethernet v2 Driver
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|  *
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|  * Copyright (c) 2017, Applied Micro Circuits Corporation
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|  * Author(s): Iyappan Subramanian <isubramanian@apm.com>
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|  *	      Keyur Chudgar <kchudgar@apm.com>
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|  */
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| 
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| #ifndef __XGENE_ENET_V2_RING_H__
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| #define __XGENE_ENET_V2_RING_H__
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| 
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| #define XGENE_ENET_DESC_SIZE	64
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| #define XGENE_ENET_NUM_DESC	256
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| #define NUM_BUFS		8
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| #define SLOT_EMPTY		0xfff
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| 
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| #define DMATXCTRL		0xa180
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| #define DMATXDESCL		0xa184
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| #define DMATXDESCH		0xa1a0
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| #define DMATXSTATUS		0xa188
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| #define DMARXCTRL		0xa18c
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| #define DMARXDESCL		0xa190
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| #define DMARXDESCH		0xa1a4
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| #define DMARXSTATUS		0xa194
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| #define DMAINTRMASK		0xa198
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| #define DMAINTERRUPT		0xa19c
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| 
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| #define D_POS			62
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| #define D_LEN			2
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| #define E_POS			63
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| #define E_LEN			1
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| #define PKT_ADDRL_POS		0
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| #define PKT_ADDRL_LEN		32
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| #define PKT_ADDRH_POS		32
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| #define PKT_ADDRH_LEN		10
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| #define PKT_SIZE_POS		32
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| #define PKT_SIZE_LEN		12
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| #define NEXT_DESC_ADDRL_POS	0
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| #define NEXT_DESC_ADDRL_LEN	32
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| #define NEXT_DESC_ADDRH_POS	48
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| #define NEXT_DESC_ADDRH_LEN	10
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| 
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| #define TXPKTCOUNT_POS		16
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| #define TXPKTCOUNT_LEN		8
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| #define RXPKTCOUNT_POS		16
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| #define RXPKTCOUNT_LEN		8
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| 
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| #define TX_PKT_SENT		BIT(0)
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| #define TX_BUS_ERROR		BIT(3)
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| #define RX_PKT_RCVD		BIT(4)
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| #define RX_BUS_ERROR		BIT(7)
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| #define RXSTATUS_RXPKTRCVD	BIT(0)
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| 
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| struct xge_raw_desc {
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| 	__le64 m0;
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| 	__le64 m1;
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| 	__le64 m2;
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| 	__le64 m3;
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| 	__le64 m4;
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| 	__le64 m5;
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| 	__le64 m6;
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| 	__le64 m7;
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| };
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| 
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| struct pkt_info {
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| 	struct sk_buff *skb;
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| 	dma_addr_t dma_addr;
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| 	void *pkt_buf;
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| };
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| 
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| /* software context of a descriptor ring */
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| struct xge_desc_ring {
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| 	struct net_device *ndev;
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| 	dma_addr_t dma_addr;
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| 	u8 head;
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| 	u8 tail;
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| 	union {
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| 		void *desc_addr;
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| 		struct xge_raw_desc *raw_desc;
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| 	};
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| 	struct pkt_info (*pkt_info);
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| };
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| 
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| static inline u64 xge_set_desc_bits(int pos, int len, u64 val)
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| {
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| 	return (val & ((1ULL << len) - 1)) << pos;
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| }
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| 
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| static inline u64 xge_get_desc_bits(int pos, int len, u64 src)
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| {
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| 	return (src >> pos) & ((1ULL << len) - 1);
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| }
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| 
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| #define SET_BITS(field, val) \
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| 		xge_set_desc_bits(field ## _POS, field ## _LEN, val)
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| 
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| #define GET_BITS(field, src) \
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| 		xge_get_desc_bits(field ## _POS, field ## _LEN, src)
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| 
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| void xge_setup_desc(struct xge_desc_ring *ring);
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| void xge_update_tx_desc_addr(struct xge_pdata *pdata);
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| void xge_update_rx_desc_addr(struct xge_pdata *pdata);
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| void xge_intr_enable(struct xge_pdata *pdata);
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| void xge_intr_disable(struct xge_pdata *pdata);
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| 
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| #endif  /* __XGENE_ENET_V2_RING_H__ */
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