77 lines
1.2 KiB
ArmAsm
77 lines
1.2 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2006-2007 PA Semi, Inc
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*
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* Maintained by: Olof Johansson <olof@lixom.net>
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*/
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/ppc_asm.h>
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#include <asm/cputable.h>
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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/* Power savings opcodes since not all binutils have them at this time */
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#define DOZE .long 0x4c000324
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#define NAP .long 0x4c000364
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#define SLEEP .long 0x4c0003a4
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#define RVW .long 0x4c0003e4
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/* Common sequence to do before going to any of the
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* powersavings modes.
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*/
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#define PRE_SLEEP_SEQUENCE \
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std r3,8(r1); \
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ptesync ; \
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ld r3,8(r1); \
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1: cmpd r3,r3; \
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bne 1b
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_doze:
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PRE_SLEEP_SEQUENCE
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DOZE
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b .
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_GLOBAL(idle_spin)
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blr
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_GLOBAL(idle_doze)
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LOAD_REG_ADDR(r3, _doze)
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b sleep_common
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/* Add more modes here later */
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sleep_common:
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mflr r0
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std r0, 16(r1)
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stdu r1,-64(r1)
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#ifdef CONFIG_PPC_PASEMI_CPUFREQ
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std r3, 48(r1)
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/* Only do power savings when in astate 0 */
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bl check_astate
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cmpwi r3,0
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bne 1f
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ld r3, 48(r1)
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#endif
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LOAD_REG_IMMEDIATE(r6,MSR_DR|MSR_IR|MSR_ME|MSR_EE)
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mfmsr r4
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andc r5,r4,r6
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mtmsrd r5,0
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mtctr r3
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bctrl
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mtmsrd r4,0
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1: addi r1,r1,64
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ld r0,16(r1)
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mtlr r0
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blr
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