173 lines
3.9 KiB
C
173 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __ASM_POWERPC_IMC_PMU_H
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#define __ASM_POWERPC_IMC_PMU_H
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/*
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* IMC Nest Performance Monitor counter support.
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*
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* Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
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* (C) 2017 Anju T Sudhakar, IBM Corporation.
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* (C) 2017 Hemant K Shaw, IBM Corporation.
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*/
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#include <linux/perf_event.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/io.h>
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#include <asm/opal.h>
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/*
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* Compatibility macros for IMC devices
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*/
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#define IMC_DTB_COMPAT "ibm,opal-in-memory-counters"
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#define IMC_DTB_UNIT_COMPAT "ibm,imc-counters"
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/*
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* LDBAR: Counter address and Enable/Disable macro.
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* perf/imc-pmu.c has the LDBAR layout information.
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*/
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#define THREAD_IMC_LDBAR_MASK 0x0003ffffffffe000ULL
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#define THREAD_IMC_ENABLE 0x8000000000000000ULL
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#define TRACE_IMC_ENABLE 0x4000000000000000ULL
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/*
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* For debugfs interface for imc-mode and imc-command
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*/
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#define IMC_CNTL_BLK_OFFSET 0x3FC00
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#define IMC_CNTL_BLK_CMD_OFFSET 8
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#define IMC_CNTL_BLK_MODE_OFFSET 32
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/*
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* Structure to hold memory address information for imc units.
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*/
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struct imc_mem_info {
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u64 *vbase;
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u32 id;
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};
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/*
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* Place holder for nest pmu events and values.
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*/
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struct imc_events {
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u32 value;
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char *name;
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char *unit;
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char *scale;
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};
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/*
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* Trace IMC hardware updates a 64bytes record on
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* Core Performance Monitoring Counter (CPMC)
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* overflow. Here is the layout for the trace imc record
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*
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* DW 0 : Timebase
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* DW 1 : Program Counter
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* DW 2 : PIDR information
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* DW 3 : CPMC1
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* DW 4 : CPMC2
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* DW 5 : CPMC3
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* Dw 6 : CPMC4
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* DW 7 : Timebase
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* .....
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*
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* The following is the data structure to hold trace imc data.
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*/
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struct trace_imc_data {
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__be64 tb1;
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__be64 ip;
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__be64 val;
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__be64 cpmc1;
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__be64 cpmc2;
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__be64 cpmc3;
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__be64 cpmc4;
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__be64 tb2;
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};
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/* Event attribute array index */
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#define IMC_FORMAT_ATTR 0
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#define IMC_EVENT_ATTR 1
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#define IMC_CPUMASK_ATTR 2
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#define IMC_NULL_ATTR 3
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/* PMU Format attribute macros */
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#define IMC_EVENT_OFFSET_MASK 0xffffffffULL
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/*
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* Macro to mask bits 0:21 of first double word(which is the timebase) to
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* compare with 8th double word (timebase) of trace imc record data.
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*/
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#define IMC_TRACE_RECORD_TB1_MASK 0x3ffffffffffULL
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/*
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* Bit 0:1 in third DW of IMC trace record
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* specifies the MSR[HV PR] values.
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*/
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#define IMC_TRACE_RECORD_VAL_HVPR(x) ((x) >> 62)
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/*
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* Device tree parser code detects IMC pmu support and
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* registers new IMC pmus. This structure will hold the
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* pmu functions, events, counter memory information
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* and attrs for each imc pmu and will be referenced at
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* the time of pmu registration.
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*/
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struct imc_pmu {
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struct pmu pmu;
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struct imc_mem_info *mem_info;
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struct imc_events *events;
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/*
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* Attribute groups for the PMU. Slot 0 used for
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* format attribute, slot 1 used for cpusmask attribute,
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* slot 2 used for event attribute. Slot 3 keep as
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* NULL.
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*/
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const struct attribute_group *attr_groups[4];
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u32 counter_mem_size;
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int domain;
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/*
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* flag to notify whether the memory is mmaped
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* or allocated by kernel.
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*/
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bool imc_counter_mmaped;
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};
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/*
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* Structure to hold id, lock and reference count for the imc events which
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* are inited.
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*/
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struct imc_pmu_ref {
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spinlock_t lock;
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unsigned int id;
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int refc;
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};
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/*
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* In-Memory Collection Counters type.
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* Data comes from Device tree.
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* Three device type are supported.
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*/
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enum {
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IMC_TYPE_THREAD = 0x1,
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IMC_TYPE_TRACE = 0x2,
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IMC_TYPE_CORE = 0x4,
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IMC_TYPE_CHIP = 0x10,
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};
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/*
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* Domains for IMC PMUs
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*/
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#define IMC_DOMAIN_NEST 1
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#define IMC_DOMAIN_CORE 2
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#define IMC_DOMAIN_THREAD 3
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/* For trace-imc the domain is still thread but it operates in trace-mode */
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#define IMC_DOMAIN_TRACE 4
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extern int init_imc_pmu(struct device_node *parent,
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struct imc_pmu *pmu_ptr, int pmu_id);
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extern void thread_imc_disable(void);
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extern int get_max_nest_dev(void);
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extern void unregister_thread_imc(void);
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#endif /* __ASM_POWERPC_IMC_PMU_H */
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