81 lines
2.0 KiB
C
81 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
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* Synopsys DesignWare XPCS helpers
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*/
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#ifndef __LINUX_PCS_XPCS_H
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#define __LINUX_PCS_XPCS_H
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#include <linux/clk.h>
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#include <linux/fwnode.h>
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#include <linux/mdio.h>
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#include <linux/phy.h>
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#include <linux/phylink.h>
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#include <linux/types.h>
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/* AN mode */
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#define DW_AN_C73 1
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#define DW_AN_C37_SGMII 2
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#define DW_2500BASEX 3
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#define DW_AN_C37_1000BASEX 4
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#define DW_10GBASER 5
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struct dw_xpcs_desc;
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enum dw_xpcs_pcs_id {
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DW_XPCS_ID_NATIVE = 0,
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NXP_SJA1105_XPCS_ID = 0x00000010,
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NXP_SJA1110_XPCS_ID = 0x00000020,
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DW_XPCS_ID = 0x7996ced0,
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DW_XPCS_ID_MASK = 0xffffffff,
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};
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enum dw_xpcs_pma_id {
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DW_XPCS_PMA_ID_NATIVE = 0,
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DW_XPCS_PMA_GEN1_3G_ID,
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DW_XPCS_PMA_GEN2_3G_ID,
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DW_XPCS_PMA_GEN2_6G_ID,
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DW_XPCS_PMA_GEN4_3G_ID,
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DW_XPCS_PMA_GEN4_6G_ID,
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DW_XPCS_PMA_GEN5_10G_ID,
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DW_XPCS_PMA_GEN5_12G_ID,
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WX_TXGBE_XPCS_PMA_10G_ID = 0x0018fc80,
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};
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struct dw_xpcs_info {
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u32 pcs;
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u32 pma;
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};
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enum dw_xpcs_clock {
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DW_XPCS_CORE_CLK,
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DW_XPCS_PAD_CLK,
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DW_XPCS_NUM_CLKS,
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};
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struct dw_xpcs {
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struct dw_xpcs_info info;
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const struct dw_xpcs_desc *desc;
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struct mdio_device *mdiodev;
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struct clk_bulk_data clks[DW_XPCS_NUM_CLKS];
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struct phylink_pcs pcs;
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phy_interface_t interface;
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};
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int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface);
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void xpcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
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phy_interface_t interface, int speed, int duplex);
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int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
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const unsigned long *advertising, unsigned int neg_mode);
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void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces);
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int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns,
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int enable);
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struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr,
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phy_interface_t interface);
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struct dw_xpcs *xpcs_create_fwnode(struct fwnode_handle *fwnode,
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phy_interface_t interface);
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void xpcs_destroy(struct dw_xpcs *xpcs);
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#endif /* __LINUX_PCS_XPCS_H */
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