576 lines
13 KiB
C
576 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) ST Ericsson SA 2011
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*
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* STE Ux500 PRCMU API
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*/
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#ifndef __MACH_PRCMU_H
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#define __MACH_PRCMU_H
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#include <linux/interrupt.h>
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#include <linux/notifier.h>
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#include <linux/err.h>
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#include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */
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/* Offset for the firmware version within the TCPM */
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#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
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#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8
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/* PRCMU Wakeup defines */
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enum prcmu_wakeup_index {
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PRCMU_WAKEUP_INDEX_RTC,
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PRCMU_WAKEUP_INDEX_RTT0,
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PRCMU_WAKEUP_INDEX_RTT1,
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PRCMU_WAKEUP_INDEX_HSI0,
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PRCMU_WAKEUP_INDEX_HSI1,
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PRCMU_WAKEUP_INDEX_USB,
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PRCMU_WAKEUP_INDEX_ABB,
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PRCMU_WAKEUP_INDEX_ABB_FIFO,
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PRCMU_WAKEUP_INDEX_ARM,
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PRCMU_WAKEUP_INDEX_CD_IRQ,
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NUM_PRCMU_WAKEUP_INDICES
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};
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#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
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/* EPOD (power domain) IDs */
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/*
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* DB8500 EPODs
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* - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
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* - EPOD_ID_SVAPIPE: power domain for SVA pipe
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* - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
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* - EPOD_ID_SIAPIPE: power domain for SIA pipe
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* - EPOD_ID_SGA: power domain for SGA
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* - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
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* - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
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* - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
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* - NUM_EPOD_ID: number of power domains
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*
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* TODO: These should be prefixed.
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*/
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#define EPOD_ID_SVAMMDSP 0
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#define EPOD_ID_SVAPIPE 1
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#define EPOD_ID_SIAMMDSP 2
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#define EPOD_ID_SIAPIPE 3
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#define EPOD_ID_SGA 4
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#define EPOD_ID_B2R2_MCDE 5
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#define EPOD_ID_ESRAM12 6
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#define EPOD_ID_ESRAM34 7
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#define NUM_EPOD_ID 8
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/*
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* state definition for EPOD (power domain)
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* - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
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* - EPOD_STATE_OFF: The EPOD is switched off
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* - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
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* retention
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* - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
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* - EPOD_STATE_ON: Same as above, but with clock enabled
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*/
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#define EPOD_STATE_NO_CHANGE 0x00
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#define EPOD_STATE_OFF 0x01
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#define EPOD_STATE_RAMRET 0x02
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#define EPOD_STATE_ON_CLK_OFF 0x03
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#define EPOD_STATE_ON 0x04
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/*
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* CLKOUT sources
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*/
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#define PRCMU_CLKSRC_CLK38M 0x00
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#define PRCMU_CLKSRC_ACLK 0x01
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#define PRCMU_CLKSRC_SYSCLK 0x02
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#define PRCMU_CLKSRC_LCDCLK 0x03
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#define PRCMU_CLKSRC_SDMMCCLK 0x04
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#define PRCMU_CLKSRC_TVCLK 0x05
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#define PRCMU_CLKSRC_TIMCLK 0x06
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#define PRCMU_CLKSRC_CLK009 0x07
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/* These are only valid for CLKOUT1: */
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#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
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#define PRCMU_CLKSRC_I2CCLK 0x41
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#define PRCMU_CLKSRC_MSP02CLK 0x42
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#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
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#define PRCMU_CLKSRC_HSIRXCLK 0x44
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#define PRCMU_CLKSRC_HSITXCLK 0x45
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#define PRCMU_CLKSRC_ARMCLKFIX 0x46
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#define PRCMU_CLKSRC_HDMICLK 0x47
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/**
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* enum prcmu_wdog_id - PRCMU watchdog IDs
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* @PRCMU_WDOG_ALL: use all timers
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* @PRCMU_WDOG_CPU1: use first CPU timer only
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* @PRCMU_WDOG_CPU2: use second CPU timer conly
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*/
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enum prcmu_wdog_id {
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PRCMU_WDOG_ALL = 0x00,
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PRCMU_WDOG_CPU1 = 0x01,
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PRCMU_WDOG_CPU2 = 0x02,
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};
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/**
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* enum ape_opp - APE OPP states definition
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* @APE_OPP_INIT:
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* @APE_NO_CHANGE: The APE operating point is unchanged
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* @APE_100_OPP: The new APE operating point is ape100opp
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* @APE_50_OPP: 50%
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* @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
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*/
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enum ape_opp {
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APE_OPP_INIT = 0x00,
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APE_NO_CHANGE = 0x01,
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APE_100_OPP = 0x02,
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APE_50_OPP = 0x03,
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APE_50_PARTLY_25_OPP = 0xFF,
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};
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/**
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* enum arm_opp - ARM OPP states definition
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* @ARM_OPP_INIT:
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* @ARM_NO_CHANGE: The ARM operating point is unchanged
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* @ARM_100_OPP: The new ARM operating point is arm100opp
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* @ARM_50_OPP: The new ARM operating point is arm50opp
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* @ARM_MAX_OPP: Operating point is "max" (more than 100)
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* @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
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* @ARM_EXTCLK: The new ARM operating point is armExtClk
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*/
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enum arm_opp {
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ARM_OPP_INIT = 0x00,
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ARM_NO_CHANGE = 0x01,
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ARM_100_OPP = 0x02,
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ARM_50_OPP = 0x03,
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ARM_MAX_OPP = 0x04,
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ARM_MAX_FREQ100OPP = 0x05,
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ARM_EXTCLK = 0x07
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};
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/**
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* enum ddr_opp - DDR OPP states definition
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* @DDR_100_OPP: The new DDR operating point is ddr100opp
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* @DDR_50_OPP: The new DDR operating point is ddr50opp
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* @DDR_25_OPP: The new DDR operating point is ddr25opp
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*/
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enum ddr_opp {
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DDR_100_OPP = 0x00,
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DDR_50_OPP = 0x01,
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DDR_25_OPP = 0x02,
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};
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/*
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* Definitions for controlling ESRAM0 in deep sleep.
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*/
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#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
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#define ESRAM0_DEEP_SLEEP_STATE_RET 2
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/**
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* enum ddr_pwrst - DDR power states definition
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* @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
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* @DDR_PWR_STATE_ON:
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* @DDR_PWR_STATE_OFFLOWLAT:
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* @DDR_PWR_STATE_OFFHIGHLAT:
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*/
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enum ddr_pwrst {
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DDR_PWR_STATE_UNCHANGED = 0x00,
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DDR_PWR_STATE_ON = 0x01,
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DDR_PWR_STATE_OFFLOWLAT = 0x02,
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DDR_PWR_STATE_OFFHIGHLAT = 0x03
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};
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#define DB8500_PRCMU_LEGACY_OFFSET 0xDD4
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#define PRCMU_FW_PROJECT_U8500 2
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#define PRCMU_FW_PROJECT_U8400 3
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#define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */
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#define PRCMU_FW_PROJECT_U8500_MBB 5
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#define PRCMU_FW_PROJECT_U8500_C1 6
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#define PRCMU_FW_PROJECT_U8500_C2 7
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#define PRCMU_FW_PROJECT_U8500_C3 8
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#define PRCMU_FW_PROJECT_U8500_C4 9
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#define PRCMU_FW_PROJECT_U9500_MBL 10
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#define PRCMU_FW_PROJECT_U8500_SSG1 11 /* Samsung specific */
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#define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */
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#define PRCMU_FW_PROJECT_U8520 13
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#define PRCMU_FW_PROJECT_U8420 14
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#define PRCMU_FW_PROJECT_U8500_SSG2 15 /* Samsung specific */
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#define PRCMU_FW_PROJECT_U8420_SYSCLK 17
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#define PRCMU_FW_PROJECT_A9420 20
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/* [32..63] 9540 and derivatives */
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#define PRCMU_FW_PROJECT_U9540 32
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/* [64..95] 8540 and derivatives */
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#define PRCMU_FW_PROJECT_L8540 64
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/* [96..126] 8580 and derivatives */
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#define PRCMU_FW_PROJECT_L8580 96
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#define PRCMU_FW_PROJECT_NAME_LEN 20
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struct prcmu_fw_version {
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u32 project; /* Notice, project shifted with 8 on ux540 */
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u8 api_version;
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u8 func_version;
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u8 errata;
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char project_name[PRCMU_FW_PROJECT_NAME_LEN];
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};
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#include <linux/mfd/db8500-prcmu.h>
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#if defined(CONFIG_UX500_SOC_DB8500)
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static inline void prcmu_early_init(void)
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{
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return db8500_prcmu_early_init();
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}
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static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
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bool keep_ap_pll)
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{
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return db8500_prcmu_set_power_state(state, keep_ulp_clk,
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keep_ap_pll);
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}
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static inline u8 prcmu_get_power_state_result(void)
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{
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return db8500_prcmu_get_power_state_result();
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}
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static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
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{
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return db8500_prcmu_set_epod(epod_id, epod_state);
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}
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static inline void prcmu_enable_wakeups(u32 wakeups)
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{
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db8500_prcmu_enable_wakeups(wakeups);
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}
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static inline void prcmu_disable_wakeups(void)
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{
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prcmu_enable_wakeups(0);
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}
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static inline void prcmu_config_abb_event_readout(u32 abb_events)
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{
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db8500_prcmu_config_abb_event_readout(abb_events);
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}
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static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
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{
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db8500_prcmu_get_abb_event_buffer(buf);
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}
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int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
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int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
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int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
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int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
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static inline int prcmu_request_clock(u8 clock, bool enable)
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{
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return db8500_prcmu_request_clock(clock, enable);
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}
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unsigned long prcmu_clock_rate(u8 clock);
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long prcmu_round_clock_rate(u8 clock, unsigned long rate);
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int prcmu_set_clock_rate(u8 clock, unsigned long rate);
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static inline int prcmu_get_ddr_opp(void)
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{
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return db8500_prcmu_get_ddr_opp();
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}
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static inline int prcmu_set_arm_opp(u8 opp)
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{
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return db8500_prcmu_set_arm_opp(opp);
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}
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static inline int prcmu_get_arm_opp(void)
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{
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return db8500_prcmu_get_arm_opp();
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}
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static inline int prcmu_set_ape_opp(u8 opp)
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{
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return db8500_prcmu_set_ape_opp(opp);
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}
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static inline int prcmu_get_ape_opp(void)
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{
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return db8500_prcmu_get_ape_opp();
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}
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static inline int prcmu_request_ape_opp_100_voltage(bool enable)
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{
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return db8500_prcmu_request_ape_opp_100_voltage(enable);
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}
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static inline void prcmu_system_reset(u16 reset_code)
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{
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return db8500_prcmu_system_reset(reset_code);
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}
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static inline u16 prcmu_get_reset_code(void)
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{
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return db8500_prcmu_get_reset_code();
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}
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int prcmu_ac_wake_req(void);
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void prcmu_ac_sleep_req(void);
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static inline void prcmu_modem_reset(void)
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{
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return db8500_prcmu_modem_reset();
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}
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static inline bool prcmu_is_ac_wake_requested(void)
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{
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return db8500_prcmu_is_ac_wake_requested();
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}
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static inline int prcmu_config_esram0_deep_sleep(u8 state)
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{
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return db8500_prcmu_config_esram0_deep_sleep(state);
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}
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static inline int prcmu_config_hotdog(u8 threshold)
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{
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return db8500_prcmu_config_hotdog(threshold);
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}
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static inline int prcmu_config_hotmon(u8 low, u8 high)
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{
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return db8500_prcmu_config_hotmon(low, high);
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}
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static inline int prcmu_start_temp_sense(u16 cycles32k)
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{
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return db8500_prcmu_start_temp_sense(cycles32k);
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}
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static inline int prcmu_stop_temp_sense(void)
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{
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return db8500_prcmu_stop_temp_sense();
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}
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static inline u32 prcmu_read(unsigned int reg)
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{
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return db8500_prcmu_read(reg);
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}
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static inline void prcmu_write(unsigned int reg, u32 value)
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{
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db8500_prcmu_write(reg, value);
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}
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static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
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{
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db8500_prcmu_write_masked(reg, mask, value);
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}
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static inline int prcmu_enable_a9wdog(u8 id)
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{
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return db8500_prcmu_enable_a9wdog(id);
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}
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static inline int prcmu_disable_a9wdog(u8 id)
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{
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return db8500_prcmu_disable_a9wdog(id);
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}
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static inline int prcmu_kick_a9wdog(u8 id)
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{
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return db8500_prcmu_kick_a9wdog(id);
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}
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static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
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{
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return db8500_prcmu_load_a9wdog(id, timeout);
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}
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static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
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{
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return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
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}
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#else
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static inline void prcmu_early_init(void) {}
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static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
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bool keep_ap_pll)
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{
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return 0;
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}
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static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
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{
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return 0;
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}
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static inline void prcmu_enable_wakeups(u32 wakeups) {}
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static inline void prcmu_disable_wakeups(void) {}
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static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
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{
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return -ENOSYS;
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}
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static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
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{
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return -ENOSYS;
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}
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static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
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u8 size)
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{
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return -ENOSYS;
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}
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static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
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{
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return 0;
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}
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static inline int prcmu_request_clock(u8 clock, bool enable)
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{
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return 0;
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}
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static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
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{
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return 0;
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}
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static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
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{
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return 0;
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}
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static inline unsigned long prcmu_clock_rate(u8 clock)
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{
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return 0;
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}
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static inline int prcmu_set_ape_opp(u8 opp)
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{
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return 0;
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}
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static inline int prcmu_get_ape_opp(void)
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{
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return APE_100_OPP;
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}
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static inline int prcmu_request_ape_opp_100_voltage(bool enable)
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{
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return 0;
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}
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static inline int prcmu_set_arm_opp(u8 opp)
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{
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return 0;
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}
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static inline int prcmu_get_arm_opp(void)
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{
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return ARM_100_OPP;
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}
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static inline int prcmu_get_ddr_opp(void)
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{
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return DDR_100_OPP;
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}
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static inline void prcmu_system_reset(u16 reset_code) {}
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static inline u16 prcmu_get_reset_code(void)
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{
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return 0;
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}
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static inline int prcmu_ac_wake_req(void)
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{
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return 0;
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}
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static inline void prcmu_ac_sleep_req(void) {}
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static inline void prcmu_modem_reset(void) {}
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static inline bool prcmu_is_ac_wake_requested(void)
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{
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return false;
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}
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static inline int prcmu_config_esram0_deep_sleep(u8 state)
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{
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return 0;
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}
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static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
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static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
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{
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*buf = NULL;
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}
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static inline int prcmu_config_hotdog(u8 threshold)
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{
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return 0;
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}
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static inline int prcmu_config_hotmon(u8 low, u8 high)
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{
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|
return 0;
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}
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static inline int prcmu_start_temp_sense(u16 cycles32k)
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{
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|
return 0;
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|
}
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static inline int prcmu_stop_temp_sense(void)
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|
{
|
|
return 0;
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}
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|
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static inline u32 prcmu_read(unsigned int reg)
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|
{
|
|
return 0;
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}
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|
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static inline void prcmu_write(unsigned int reg, u32 value) {}
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|
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static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
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#endif
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static inline void prcmu_set(unsigned int reg, u32 bits)
|
|
{
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prcmu_write_masked(reg, bits, bits);
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}
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|
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static inline void prcmu_clear(unsigned int reg, u32 bits)
|
|
{
|
|
prcmu_write_masked(reg, bits, 0);
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|
}
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|
|
|
/* PRCMU QoS APE OPP class */
|
|
#define PRCMU_QOS_APE_OPP 1
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|
#define PRCMU_QOS_DDR_OPP 2
|
|
#define PRCMU_QOS_ARM_OPP 3
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|
#define PRCMU_QOS_DEFAULT_VALUE -1
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|
|
|
static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
|
|
char *name, s32 value)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
|
|
char *name, s32 new_value)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
|
|
{
|
|
}
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|
|
|
#endif /* __MACH_PRCMU_H */
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