371 lines
9.8 KiB
C
371 lines
9.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Marvell 88PM80x Interface
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*
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* Copyright (C) 2012 Marvell International Ltd.
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* Qiao Zhou <zhouqiao@marvell.com>
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*/
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#ifndef __LINUX_MFD_88PM80X_H
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#define __LINUX_MFD_88PM80X_H
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/regmap.h>
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#include <linux/atomic.h>
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enum {
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CHIP_INVALID = 0,
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CHIP_PM800,
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CHIP_PM805,
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CHIP_PM860,
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CHIP_MAX,
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};
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enum {
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PM800_ID_BUCK1 = 0,
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PM800_ID_BUCK2,
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PM800_ID_BUCK3,
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PM800_ID_BUCK4,
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PM800_ID_BUCK5,
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PM800_ID_LDO1,
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PM800_ID_LDO2,
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PM800_ID_LDO3,
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PM800_ID_LDO4,
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PM800_ID_LDO5,
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PM800_ID_LDO6,
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PM800_ID_LDO7,
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PM800_ID_LDO8,
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PM800_ID_LDO9,
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PM800_ID_LDO10,
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PM800_ID_LDO11,
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PM800_ID_LDO12,
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PM800_ID_LDO13,
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PM800_ID_LDO14,
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PM800_ID_LDO15,
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PM800_ID_LDO16,
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PM800_ID_LDO17,
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PM800_ID_LDO18,
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PM800_ID_LDO19,
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PM800_ID_RG_MAX,
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};
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#define PM800_MAX_REGULATOR PM800_ID_RG_MAX /* 5 Bucks, 19 LDOs */
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#define PM800_NUM_BUCK (5) /*5 Bucks */
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#define PM800_NUM_LDO (19) /*19 Bucks */
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/* page 0 basic: slave adder 0x60 */
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#define PM800_STATUS_1 (0x01)
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#define PM800_ONKEY_STS1 BIT(0)
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#define PM800_EXTON_STS1 BIT(1)
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#define PM800_CHG_STS1 BIT(2)
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#define PM800_BAT_STS1 BIT(3)
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#define PM800_VBUS_STS1 BIT(4)
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#define PM800_LDO_PGOOD_STS1 BIT(5)
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#define PM800_BUCK_PGOOD_STS1 BIT(6)
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#define PM800_STATUS_2 (0x02)
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#define PM800_RTC_ALARM_STS2 BIT(0)
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/* Wakeup Registers */
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#define PM800_WAKEUP1 (0x0D)
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#define PM800_WAKEUP2 (0x0E)
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#define PM800_WAKEUP2_INV_INT BIT(0)
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#define PM800_WAKEUP2_INT_CLEAR BIT(1)
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#define PM800_WAKEUP2_INT_MASK BIT(2)
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#define PM800_POWER_UP_LOG (0x10)
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/* Referance and low power registers */
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#define PM800_LOW_POWER1 (0x20)
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#define PM800_LOW_POWER2 (0x21)
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#define PM800_LOW_POWER_CONFIG3 (0x22)
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#define PM800_LOW_POWER_CONFIG4 (0x23)
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/* GPIO register */
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#define PM800_GPIO_0_1_CNTRL (0x30)
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#define PM800_GPIO0_VAL BIT(0)
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#define PM800_GPIO0_GPIO_MODE(x) (x << 1)
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#define PM800_GPIO1_VAL BIT(4)
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#define PM800_GPIO1_GPIO_MODE(x) (x << 5)
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#define PM800_GPIO_2_3_CNTRL (0x31)
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#define PM800_GPIO2_VAL BIT(0)
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#define PM800_GPIO2_GPIO_MODE(x) (x << 1)
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#define PM800_GPIO3_VAL BIT(4)
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#define PM800_GPIO3_GPIO_MODE(x) (x << 5)
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#define PM800_GPIO3_MODE_MASK 0x1F
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#define PM800_GPIO3_HEADSET_MODE PM800_GPIO3_GPIO_MODE(6)
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#define PM800_GPIO_4_CNTRL (0x32)
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#define PM800_GPIO4_VAL BIT(0)
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#define PM800_GPIO4_GPIO_MODE(x) (x << 1)
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#define PM800_HEADSET_CNTRL (0x38)
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#define PM800_HEADSET_DET_EN BIT(7)
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#define PM800_HSDET_SLP BIT(1)
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/* PWM register */
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#define PM800_PWM1 (0x40)
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#define PM800_PWM2 (0x41)
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#define PM800_PWM3 (0x42)
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#define PM800_PWM4 (0x43)
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/* RTC Registers */
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#define PM800_RTC_CONTROL (0xD0)
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#define PM800_RTC_MISC1 (0xE1)
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#define PM800_RTC_MISC2 (0xE2)
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#define PM800_RTC_MISC3 (0xE3)
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#define PM800_RTC_MISC4 (0xE4)
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#define PM800_RTC_MISC5 (0xE7)
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/* bit definitions of RTC Register 1 (0xD0) */
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#define PM800_ALARM1_EN BIT(0)
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#define PM800_ALARM_WAKEUP BIT(4)
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#define PM800_ALARM BIT(5)
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#define PM800_RTC1_USE_XO BIT(7)
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/* Regulator Control Registers: BUCK1,BUCK5,LDO1 have DVC */
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/* buck registers */
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#define PM800_SLEEP_BUCK1 (0x30)
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/* BUCK Sleep Mode Register 1: BUCK[1..4] */
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#define PM800_BUCK_SLP1 (0x5A)
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#define PM800_BUCK1_SLP1_SHIFT 0
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#define PM800_BUCK1_SLP1_MASK (0x3 << PM800_BUCK1_SLP1_SHIFT)
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/* page 2 GPADC: slave adder 0x02 */
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#define PM800_GPADC_MEAS_EN1 (0x01)
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#define PM800_MEAS_EN1_VBAT BIT(2)
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#define PM800_GPADC_MEAS_EN2 (0x02)
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#define PM800_MEAS_EN2_RFTMP BIT(0)
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#define PM800_MEAS_GP0_EN BIT(2)
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#define PM800_MEAS_GP1_EN BIT(3)
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#define PM800_MEAS_GP2_EN BIT(4)
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#define PM800_MEAS_GP3_EN BIT(5)
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#define PM800_MEAS_GP4_EN BIT(6)
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#define PM800_GPADC_MISC_CONFIG1 (0x05)
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#define PM800_GPADC_MISC_CONFIG2 (0x06)
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#define PM800_GPADC_MISC_GPFSM_EN BIT(0)
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#define PM800_GPADC_SLOW_MODE(x) (x << 3)
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#define PM800_GPADC_MISC_CONFIG3 (0x09)
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#define PM800_GPADC_MISC_CONFIG4 (0x0A)
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#define PM800_GPADC_PREBIAS1 (0x0F)
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#define PM800_GPADC0_GP_PREBIAS_TIME(x) (x << 0)
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#define PM800_GPADC_PREBIAS2 (0x10)
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#define PM800_GP_BIAS_ENA1 (0x14)
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#define PM800_GPADC_GP_BIAS_EN0 BIT(0)
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#define PM800_GPADC_GP_BIAS_EN1 BIT(1)
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#define PM800_GPADC_GP_BIAS_EN2 BIT(2)
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#define PM800_GPADC_GP_BIAS_EN3 BIT(3)
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#define PM800_GP_BIAS_OUT1 (0x15)
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#define PM800_BIAS_OUT_GP0 BIT(0)
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#define PM800_BIAS_OUT_GP1 BIT(1)
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#define PM800_BIAS_OUT_GP2 BIT(2)
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#define PM800_BIAS_OUT_GP3 BIT(3)
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#define PM800_GPADC0_LOW_TH 0x20
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#define PM800_GPADC1_LOW_TH 0x21
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#define PM800_GPADC2_LOW_TH 0x22
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#define PM800_GPADC3_LOW_TH 0x23
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#define PM800_GPADC4_LOW_TH 0x24
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#define PM800_GPADC0_UPP_TH 0x30
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#define PM800_GPADC1_UPP_TH 0x31
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#define PM800_GPADC2_UPP_TH 0x32
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#define PM800_GPADC3_UPP_TH 0x33
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#define PM800_GPADC4_UPP_TH 0x34
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#define PM800_VBBAT_MEAS1 0x40
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#define PM800_VBBAT_MEAS2 0x41
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#define PM800_VBAT_MEAS1 0x42
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#define PM800_VBAT_MEAS2 0x43
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#define PM800_VSYS_MEAS1 0x44
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#define PM800_VSYS_MEAS2 0x45
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#define PM800_VCHG_MEAS1 0x46
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#define PM800_VCHG_MEAS2 0x47
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#define PM800_TINT_MEAS1 0x50
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#define PM800_TINT_MEAS2 0x51
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#define PM800_PMOD_MEAS1 0x52
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#define PM800_PMOD_MEAS2 0x53
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#define PM800_GPADC0_MEAS1 0x54
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#define PM800_GPADC0_MEAS2 0x55
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#define PM800_GPADC1_MEAS1 0x56
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#define PM800_GPADC1_MEAS2 0x57
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#define PM800_GPADC2_MEAS1 0x58
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#define PM800_GPADC2_MEAS2 0x59
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#define PM800_GPADC3_MEAS1 0x5A
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#define PM800_GPADC3_MEAS2 0x5B
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#define PM800_GPADC4_MEAS1 0x5C
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#define PM800_GPADC4_MEAS2 0x5D
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#define PM800_GPADC4_AVG1 0xA8
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#define PM800_GPADC4_AVG2 0xA9
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/* 88PM805 Registers */
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#define PM805_MAIN_POWERUP (0x01)
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#define PM805_INT_STATUS0 (0x02) /* for ena/dis all interrupts */
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#define PM805_STATUS0_INT_CLEAR (1 << 0)
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#define PM805_STATUS0_INV_INT (1 << 1)
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#define PM800_STATUS0_INT_MASK (1 << 2)
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#define PM805_INT_STATUS1 (0x03)
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#define PM805_INT1_HP1_SHRT BIT(0)
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#define PM805_INT1_HP2_SHRT BIT(1)
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#define PM805_INT1_MIC_CONFLICT BIT(2)
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#define PM805_INT1_CLIP_FAULT BIT(3)
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#define PM805_INT1_LDO_OFF BIT(4)
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#define PM805_INT1_SRC_DPLL_LOCK BIT(5)
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#define PM805_INT_STATUS2 (0x04)
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#define PM805_INT2_MIC_DET BIT(0)
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#define PM805_INT2_SHRT_BTN_DET BIT(1)
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#define PM805_INT2_VOLM_BTN_DET BIT(2)
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#define PM805_INT2_VOLP_BTN_DET BIT(3)
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#define PM805_INT2_RAW_PLL_FAULT BIT(4)
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#define PM805_INT2_FINE_PLL_FAULT BIT(5)
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#define PM805_INT_MASK1 (0x05)
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#define PM805_INT_MASK2 (0x06)
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#define PM805_SHRT_BTN_DET BIT(1)
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/* number of status and int reg in a row */
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#define PM805_INT_REG_NUM (2)
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#define PM805_MIC_DET1 (0x07)
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#define PM805_MIC_DET_EN_MIC_DET BIT(0)
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#define PM805_MIC_DET2 (0x08)
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#define PM805_MIC_DET_STATUS1 (0x09)
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#define PM805_MIC_DET_STATUS3 (0x0A)
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#define PM805_AUTO_SEQ_STATUS1 (0x0B)
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#define PM805_AUTO_SEQ_STATUS2 (0x0C)
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#define PM805_ADC_SETTING1 (0x10)
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#define PM805_ADC_SETTING2 (0x11)
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#define PM805_ADC_SETTING3 (0x11)
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#define PM805_ADC_GAIN1 (0x12)
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#define PM805_ADC_GAIN2 (0x13)
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#define PM805_DMIC_SETTING (0x15)
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#define PM805_DWS_SETTING (0x16)
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#define PM805_MIC_CONFLICT_STS (0x17)
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#define PM805_PDM_SETTING1 (0x20)
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#define PM805_PDM_SETTING2 (0x21)
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#define PM805_PDM_SETTING3 (0x22)
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#define PM805_PDM_CONTROL1 (0x23)
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#define PM805_PDM_CONTROL2 (0x24)
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#define PM805_PDM_CONTROL3 (0x25)
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#define PM805_HEADPHONE_SETTING (0x26)
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#define PM805_HEADPHONE_GAIN_A2A (0x27)
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#define PM805_HEADPHONE_SHORT_STATE (0x28)
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#define PM805_EARPHONE_SETTING (0x29)
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#define PM805_AUTO_SEQ_SETTING (0x2A)
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struct pm80x_rtc_pdata {
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int vrtc;
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int rtc_wakeup;
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};
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struct pm80x_subchip {
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struct i2c_client *power_page; /* chip client for power page */
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struct i2c_client *gpadc_page; /* chip client for gpadc page */
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struct regmap *regmap_power;
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struct regmap *regmap_gpadc;
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unsigned short power_page_addr; /* power page I2C address */
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unsigned short gpadc_page_addr; /* gpadc page I2C address */
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};
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struct pm80x_chip {
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struct pm80x_subchip *subchip;
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struct device *dev;
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struct i2c_client *client;
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struct i2c_client *companion;
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struct regmap *regmap;
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const struct regmap_irq_chip *regmap_irq_chip;
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struct regmap_irq_chip_data *irq_data;
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int type;
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int irq;
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int irq_mode;
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unsigned long wu_flag;
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spinlock_t lock;
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};
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struct pm80x_platform_data {
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struct pm80x_rtc_pdata *rtc;
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/*
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* For the regulator not defined, set regulators[not_defined] to be
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* NULL. num_regulators are the number of regulators supposed to be
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* initialized. If all regulators are not defined, set num_regulators
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* to be 0.
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*/
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struct regulator_init_data *regulators[PM800_ID_RG_MAX];
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unsigned int num_regulators;
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int irq_mode; /* Clear interrupt by read/write(0/1) */
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int batt_det; /* enable/disable */
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int (*plat_config)(struct pm80x_chip *chip,
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struct pm80x_platform_data *pdata);
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};
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extern const struct dev_pm_ops pm80x_pm_ops;
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extern const struct regmap_config pm80x_regmap_config;
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static inline int pm80x_request_irq(struct pm80x_chip *pm80x, int irq,
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irq_handler_t handler, unsigned long flags,
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const char *name, void *data)
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{
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if (!pm80x->irq_data)
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return -EINVAL;
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return request_threaded_irq(regmap_irq_get_virq(pm80x->irq_data, irq),
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NULL, handler, flags, name, data);
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}
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static inline void pm80x_free_irq(struct pm80x_chip *pm80x, int irq, void *data)
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{
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if (!pm80x->irq_data)
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return;
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free_irq(regmap_irq_get_virq(pm80x->irq_data, irq), data);
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}
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#ifdef CONFIG_PM
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static inline int pm80x_dev_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent);
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int irq = platform_get_irq(pdev, 0);
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if (device_may_wakeup(dev))
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set_bit(irq, &chip->wu_flag);
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return 0;
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}
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static inline int pm80x_dev_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent);
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int irq = platform_get_irq(pdev, 0);
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if (device_may_wakeup(dev))
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clear_bit(irq, &chip->wu_flag);
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return 0;
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}
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#endif
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extern int pm80x_init(struct i2c_client *client);
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extern int pm80x_deinit(void);
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#endif /* __LINUX_MFD_88PM80X_H */
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