78 lines
2.1 KiB
C
78 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/*
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* cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header
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*
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* Copyright 2022 Cirrus Logic, Inc.
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*/
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#ifndef DT_CS35L45_H
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#define DT_CS35L45_H
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/*
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* cirrus,asp-sdout-hiz-ctrl
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*
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* TX_HIZ_UNUSED: TX pin high-impedance during unused slots.
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* TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.
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*/
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#define CS35L45_ASP_TX_HIZ_UNUSED 0x1
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#define CS35L45_ASP_TX_HIZ_DISABLED 0x2
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/*
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* Optional GPIOX Sub-nodes:
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* The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
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* sub-nodes for configuring the GPIO pins.
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*
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* - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
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* is 1.
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* 0 = Output
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* 1 = Input (Default)
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*
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* - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.
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*
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* 0 = Low (Default)
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* 1 = High
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*
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* - gpio-op-cfg : GPIO output configuration. Valid only when 'gpio-ctrl' is 1
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* and 'gpio-dir' is 0.
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*
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* 0 = CMOS (Default)
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* 1 = Open Drain
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*
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* - gpio-pol : GPIO output polarity select. Valid only when 'gpio-ctrl' is 1
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* and 'gpio-dir' is 0.
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*
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* 0 = Non-inverted, Active High (Default)
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* 1 = Inverted, Active Low
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*
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* - gpio-invert : Defines the polarity of the GPIO pin if configured
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* as input.
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*
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* 0 = Not inverted (Default)
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* 1 = Inverted
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*
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* - gpio-ctrl : Defines the function of the GPIO pin.
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*
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* GPIO1:
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* 0 = High impedance input (Default)
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* 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
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* 2 = Pin acts as MDSYNC, direction controlled by MDSYNC
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* 3-7 = Reserved
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*
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* GPIO2:
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* 0 = High impedance input (Default)
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* 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
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* 2 = Pin acts as open drain INT
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* 3 = Reserved
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* 4 = Pin acts as push-pull output INT. Active low.
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* 5 = Pin acts as push-pull output INT. Active high.
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* 6,7 = Reserved
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*
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* GPIO3:
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* 0 = High impedance input (Default)
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* 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
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* 2-7 = Reserved
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*/
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#define CS35L45_NUM_GPIOS 0x3
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#endif /* DT_CS35L45_H */
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