67 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			67 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0-only
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| /*
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|  * Copyright (c) 2024 AIROHA Inc
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|  * Author: Lorenzo Bianconi <lorenzo@kernel.org>
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|  */
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| 
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| #ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
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| #define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
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| 
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| /* RST_CTRL2 */
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| #define EN7581_XPON_PHY_RST		 0
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| #define EN7581_CPU_TIMER2_RST		 1
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| #define EN7581_HSUART_RST		 2
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| #define EN7581_UART4_RST		 3
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| #define EN7581_UART5_RST		 4
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| #define EN7581_I2C2_RST			 5
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| #define EN7581_XSI_MAC_RST		 6
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| #define EN7581_XSI_PHY_RST		 7
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| #define EN7581_NPU_RST			 8
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| #define EN7581_I2S_RST			 9
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| #define EN7581_TRNG_RST			10
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| #define EN7581_TRNG_MSTART_RST		11
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| #define EN7581_DUAL_HSI0_RST		12
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| #define EN7581_DUAL_HSI1_RST		13
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| #define EN7581_HSI_RST			14
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| #define EN7581_DUAL_HSI0_MAC_RST	15
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| #define EN7581_DUAL_HSI1_MAC_RST	16
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| #define EN7581_HSI_MAC_RST		17
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| #define EN7581_WDMA_RST			18
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| #define EN7581_WOE0_RST			19
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| #define EN7581_WOE1_RST			20
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| #define EN7581_HSDMA_RST		21
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| #define EN7581_TDMA_RST			22
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| #define EN7581_EMMC_RST			23
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| #define EN7581_SOE_RST			24
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| #define EN7581_PCIE2_RST		25
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| #define EN7581_XFP_MAC_RST		26
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| #define EN7581_USB_HOST_P1_RST		27
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| #define EN7581_USB_HOST_P1_U3_PHY_RST	28
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| /* RST_CTRL1 */
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| #define EN7581_PCM1_ZSI_ISI_RST		29
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| #define EN7581_FE_PDMA_RST		30
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| #define EN7581_FE_QDMA_RST		31
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| #define EN7581_PCM_SPIWP_RST		32
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| #define EN7581_CRYPTO_RST		33
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| #define EN7581_TIMER_RST		34
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| #define EN7581_PCM1_RST			35
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| #define EN7581_UART_RST			36
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| #define EN7581_GPIO_RST			37
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| #define EN7581_GDMA_RST			38
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| #define EN7581_I2C_MASTER_RST		39
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| #define EN7581_PCM2_ZSI_ISI_RST		40
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| #define EN7581_SFC_RST			41
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| #define EN7581_UART2_RST		42
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| #define EN7581_GDMP_RST			43
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| #define EN7581_FE_RST			44
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| #define EN7581_USB_HOST_P0_RST		45
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| #define EN7581_GSW_RST			46
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| #define EN7581_SFC2_PCM_RST		47
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| #define EN7581_PCIE0_RST		48
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| #define EN7581_PCIE1_RST		49
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| #define EN7581_CPU_TIMER_RST		50
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| #define EN7581_PCIE_HB_RST		51
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| #define EN7581_XPON_MAC_RST		52
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| 
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| #endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */
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