46 lines
912 B
C
46 lines
912 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Xilinx, Inc.
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*/
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#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
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#define _DT_BINDINGS_ZYNQMP_POWER_H
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#define PD_RPU_0 7
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#define PD_RPU_1 8
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#define PD_R5_0_ATCM 15
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#define PD_R5_0_BTCM 16
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#define PD_R5_1_ATCM 17
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#define PD_R5_1_BTCM 18
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#define PD_USB_0 22
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#define PD_USB_1 23
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#define PD_TTC_0 24
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#define PD_TTC_1 25
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#define PD_TTC_2 26
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#define PD_TTC_3 27
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#define PD_SATA 28
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#define PD_ETH_0 29
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#define PD_ETH_1 30
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#define PD_ETH_2 31
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#define PD_ETH_3 32
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#define PD_UART_0 33
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#define PD_UART_1 34
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#define PD_SPI_0 35
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#define PD_SPI_1 36
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#define PD_I2C_0 37
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#define PD_I2C_1 38
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#define PD_SD_0 39
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#define PD_SD_1 40
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#define PD_DP 41
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#define PD_GDMA 42
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#define PD_ADMA 43
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#define PD_NAND 44
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#define PD_QSPI 45
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#define PD_GPIO 46
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#define PD_CAN_0 47
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#define PD_CAN_1 48
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#define PD_GPU 58
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#define PD_PCIE 59
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#endif
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