89 lines
2.2 KiB
C
89 lines
2.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) Sunplus Technology Co., Ltd.
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* All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H
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#define _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H
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/* gates */
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#define CLK_RTC 0
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#define CLK_OTPRX 1
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#define CLK_NOC 2
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#define CLK_BR 3
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#define CLK_SPIFL 4
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#define CLK_PERI0 5
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#define CLK_PERI1 6
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#define CLK_STC0 7
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#define CLK_STC_AV0 8
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#define CLK_STC_AV1 9
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#define CLK_STC_AV2 10
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#define CLK_UA0 11
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#define CLK_UA1 12
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#define CLK_UA2 13
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#define CLK_UA3 14
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#define CLK_UA4 15
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#define CLK_HWUA 16
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#define CLK_DDC0 17
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#define CLK_UADMA 18
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#define CLK_CBDMA0 19
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#define CLK_CBDMA1 20
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#define CLK_SPI_COMBO_0 21
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#define CLK_SPI_COMBO_1 22
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#define CLK_SPI_COMBO_2 23
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#define CLK_SPI_COMBO_3 24
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#define CLK_AUD 25
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#define CLK_USBC0 26
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#define CLK_USBC1 27
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#define CLK_UPHY0 28
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#define CLK_UPHY1 29
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#define CLK_I2CM0 30
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#define CLK_I2CM1 31
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#define CLK_I2CM2 32
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#define CLK_I2CM3 33
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#define CLK_PMC 34
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#define CLK_CARD_CTL0 35
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#define CLK_CARD_CTL1 36
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#define CLK_CARD_CTL4 37
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#define CLK_BCH 38
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#define CLK_DDFCH 39
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#define CLK_CSIIW0 40
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#define CLK_CSIIW1 41
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#define CLK_MIPICSI0 42
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#define CLK_MIPICSI1 43
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#define CLK_HDMI_TX 44
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#define CLK_VPOST 45
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#define CLK_TGEN 46
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#define CLK_DMIX 47
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#define CLK_TCON 48
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#define CLK_GPIO 49
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#define CLK_MAILBOX 50
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#define CLK_SPIND 51
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#define CLK_I2C2CBUS 52
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#define CLK_SEC 53
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#define CLK_DVE 54
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#define CLK_GPOST0 55
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#define CLK_OSD0 56
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#define CLK_DISP_PWM 57
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#define CLK_UADBG 58
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#define CLK_FIO_CTL 59
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#define CLK_FPGA 60
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#define CLK_L2SW 61
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#define CLK_ICM 62
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#define CLK_AXI_GLOBAL 63
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/* plls */
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#define PLL_A 64
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#define PLL_E 65
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#define PLL_E_2P5 66
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#define PLL_E_25 67
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#define PLL_E_112P5 68
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#define PLL_F 69
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#define PLL_TV 70
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#define PLL_TV_A 71
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#define PLL_SYS 72
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#define CLK_MAX 73
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#endif
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