239 lines
7.5 KiB
C
239 lines
7.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
|
|
|
#ifndef _DT_BINDINGS_CLK_MSM_GCC_8953_H
|
|
#define _DT_BINDINGS_CLK_MSM_GCC_8953_H
|
|
|
|
/* Clocks */
|
|
#define APC0_DROOP_DETECTOR_CLK_SRC 0
|
|
#define APC1_DROOP_DETECTOR_CLK_SRC 1
|
|
#define APSS_AHB_CLK_SRC 2
|
|
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3
|
|
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4
|
|
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5
|
|
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6
|
|
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7
|
|
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8
|
|
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9
|
|
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10
|
|
#define BLSP1_UART1_APPS_CLK_SRC 11
|
|
#define BLSP1_UART2_APPS_CLK_SRC 12
|
|
#define BLSP2_QUP1_I2C_APPS_CLK_SRC 13
|
|
#define BLSP2_QUP1_SPI_APPS_CLK_SRC 14
|
|
#define BLSP2_QUP2_I2C_APPS_CLK_SRC 15
|
|
#define BLSP2_QUP2_SPI_APPS_CLK_SRC 16
|
|
#define BLSP2_QUP3_I2C_APPS_CLK_SRC 17
|
|
#define BLSP2_QUP3_SPI_APPS_CLK_SRC 18
|
|
#define BLSP2_QUP4_I2C_APPS_CLK_SRC 19
|
|
#define BLSP2_QUP4_SPI_APPS_CLK_SRC 20
|
|
#define BLSP2_UART1_APPS_CLK_SRC 21
|
|
#define BLSP2_UART2_APPS_CLK_SRC 22
|
|
#define BYTE0_CLK_SRC 23
|
|
#define BYTE1_CLK_SRC 24
|
|
#define CAMSS_GP0_CLK_SRC 25
|
|
#define CAMSS_GP1_CLK_SRC 26
|
|
#define CAMSS_TOP_AHB_CLK_SRC 27
|
|
#define CCI_CLK_SRC 28
|
|
#define CPP_CLK_SRC 29
|
|
#define CRYPTO_CLK_SRC 30
|
|
#define CSI0PHYTIMER_CLK_SRC 31
|
|
#define CSI0P_CLK_SRC 32
|
|
#define CSI0_CLK_SRC 33
|
|
#define CSI1PHYTIMER_CLK_SRC 34
|
|
#define CSI1P_CLK_SRC 35
|
|
#define CSI1_CLK_SRC 36
|
|
#define CSI2PHYTIMER_CLK_SRC 37
|
|
#define CSI2P_CLK_SRC 38
|
|
#define CSI2_CLK_SRC 39
|
|
#define ESC0_CLK_SRC 40
|
|
#define ESC1_CLK_SRC 41
|
|
#define GCC_APC0_DROOP_DETECTOR_GPLL0_CLK 42
|
|
#define GCC_APC1_DROOP_DETECTOR_GPLL0_CLK 43
|
|
#define GCC_APSS_AHB_CLK 44
|
|
#define GCC_APSS_AXI_CLK 45
|
|
#define GCC_APSS_TCU_ASYNC_CLK 46
|
|
#define GCC_BIMC_GFX_CLK 47
|
|
#define GCC_BIMC_GPU_CLK 48
|
|
#define GCC_BLSP1_AHB_CLK 49
|
|
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 50
|
|
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 51
|
|
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 52
|
|
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 53
|
|
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 54
|
|
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 55
|
|
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 56
|
|
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 57
|
|
#define GCC_BLSP1_UART1_APPS_CLK 58
|
|
#define GCC_BLSP1_UART2_APPS_CLK 59
|
|
#define GCC_BLSP2_AHB_CLK 60
|
|
#define GCC_BLSP2_QUP1_I2C_APPS_CLK 61
|
|
#define GCC_BLSP2_QUP1_SPI_APPS_CLK 62
|
|
#define GCC_BLSP2_QUP2_I2C_APPS_CLK 63
|
|
#define GCC_BLSP2_QUP2_SPI_APPS_CLK 64
|
|
#define GCC_BLSP2_QUP3_I2C_APPS_CLK 65
|
|
#define GCC_BLSP2_QUP3_SPI_APPS_CLK 66
|
|
#define GCC_BLSP2_QUP4_I2C_APPS_CLK 67
|
|
#define GCC_BLSP2_QUP4_SPI_APPS_CLK 68
|
|
#define GCC_BLSP2_UART1_APPS_CLK 69
|
|
#define GCC_BLSP2_UART2_APPS_CLK 70
|
|
#define GCC_BOOT_ROM_AHB_CLK 71
|
|
#define GCC_CAMSS_AHB_CLK 72
|
|
#define GCC_CAMSS_CCI_AHB_CLK 73
|
|
#define GCC_CAMSS_CCI_CLK 74
|
|
#define GCC_CAMSS_CPP_AHB_CLK 75
|
|
#define GCC_CAMSS_CPP_AXI_CLK 76
|
|
#define GCC_CAMSS_CPP_CLK 77
|
|
#define GCC_CAMSS_CSI0PHYTIMER_CLK 78
|
|
#define GCC_CAMSS_CSI0PHY_CLK 79
|
|
#define GCC_CAMSS_CSI0PIX_CLK 80
|
|
#define GCC_CAMSS_CSI0RDI_CLK 81
|
|
#define GCC_CAMSS_CSI0_AHB_CLK 82
|
|
#define GCC_CAMSS_CSI0_CLK 83
|
|
#define GCC_CAMSS_CSI0_CSIPHY_3P_CLK 84
|
|
#define GCC_CAMSS_CSI1PHYTIMER_CLK 85
|
|
#define GCC_CAMSS_CSI1PHY_CLK 86
|
|
#define GCC_CAMSS_CSI1PIX_CLK 87
|
|
#define GCC_CAMSS_CSI1RDI_CLK 88
|
|
#define GCC_CAMSS_CSI1_AHB_CLK 89
|
|
#define GCC_CAMSS_CSI1_CLK 90
|
|
#define GCC_CAMSS_CSI1_CSIPHY_3P_CLK 91
|
|
#define GCC_CAMSS_CSI2PHYTIMER_CLK 92
|
|
#define GCC_CAMSS_CSI2PHY_CLK 93
|
|
#define GCC_CAMSS_CSI2PIX_CLK 94
|
|
#define GCC_CAMSS_CSI2RDI_CLK 95
|
|
#define GCC_CAMSS_CSI2_AHB_CLK 96
|
|
#define GCC_CAMSS_CSI2_CLK 97
|
|
#define GCC_CAMSS_CSI2_CSIPHY_3P_CLK 98
|
|
#define GCC_CAMSS_CSI_VFE0_CLK 99
|
|
#define GCC_CAMSS_CSI_VFE1_CLK 100
|
|
#define GCC_CAMSS_GP0_CLK 101
|
|
#define GCC_CAMSS_GP1_CLK 102
|
|
#define GCC_CAMSS_ISPIF_AHB_CLK 103
|
|
#define GCC_CAMSS_JPEG0_CLK 104
|
|
#define GCC_CAMSS_JPEG_AHB_CLK 105
|
|
#define GCC_CAMSS_JPEG_AXI_CLK 106
|
|
#define GCC_CAMSS_MCLK0_CLK 107
|
|
#define GCC_CAMSS_MCLK1_CLK 108
|
|
#define GCC_CAMSS_MCLK2_CLK 109
|
|
#define GCC_CAMSS_MCLK3_CLK 110
|
|
#define GCC_CAMSS_MICRO_AHB_CLK 111
|
|
#define GCC_CAMSS_TOP_AHB_CLK 112
|
|
#define GCC_CAMSS_VFE0_AHB_CLK 113
|
|
#define GCC_CAMSS_VFE0_AXI_CLK 114
|
|
#define GCC_CAMSS_VFE0_CLK 115
|
|
#define GCC_CAMSS_VFE1_AHB_CLK 116
|
|
#define GCC_CAMSS_VFE1_AXI_CLK 117
|
|
#define GCC_CAMSS_VFE1_CLK 118
|
|
#define GCC_CPP_TBU_CLK 119
|
|
#define GCC_CRYPTO_AHB_CLK 120
|
|
#define GCC_CRYPTO_AXI_CLK 121
|
|
#define GCC_CRYPTO_CLK 122
|
|
#define GCC_DCC_CLK 123
|
|
#define GCC_GP1_CLK 124
|
|
#define GCC_GP2_CLK 125
|
|
#define GCC_GP3_CLK 126
|
|
#define GCC_JPEG_TBU_CLK 127
|
|
#define GCC_MDP_TBU_CLK 128
|
|
#define GCC_MDSS_AHB_CLK 129
|
|
#define GCC_MDSS_AXI_CLK 130
|
|
#define GCC_MDSS_BYTE0_CLK 131
|
|
#define GCC_MDSS_BYTE1_CLK 132
|
|
#define GCC_MDSS_ESC0_CLK 133
|
|
#define GCC_MDSS_ESC1_CLK 134
|
|
#define GCC_MDSS_MDP_CLK 135
|
|
#define GCC_MDSS_PCLK0_CLK 136
|
|
#define GCC_MDSS_PCLK1_CLK 137
|
|
#define GCC_MDSS_VSYNC_CLK 138
|
|
#define GCC_MSS_CFG_AHB_CLK 139
|
|
#define GCC_MSS_Q6_BIMC_AXI_CLK 140
|
|
#define GCC_OXILI_AHB_CLK 141
|
|
#define GCC_OXILI_AON_CLK 142
|
|
#define GCC_OXILI_GFX3D_CLK 143
|
|
#define GCC_OXILI_TIMER_CLK 144
|
|
#define GCC_PCNOC_USB3_AXI_CLK 145
|
|
#define GCC_PDM2_CLK 146
|
|
#define GCC_PDM_AHB_CLK 147
|
|
#define GCC_PRNG_AHB_CLK 148
|
|
#define GCC_QDSS_DAP_CLK 149
|
|
#define GCC_QUSB_REF_CLK 150
|
|
#define GCC_RBCPR_GFX_CLK 151
|
|
#define GCC_SDCC1_AHB_CLK 152
|
|
#define GCC_SDCC1_APPS_CLK 153
|
|
#define GCC_SDCC1_ICE_CORE_CLK 154
|
|
#define GCC_SDCC2_AHB_CLK 155
|
|
#define GCC_SDCC2_APPS_CLK 156
|
|
#define GCC_SMMU_CFG_CLK 157
|
|
#define GCC_USB30_MASTER_CLK 158
|
|
#define GCC_USB30_MOCK_UTMI_CLK 159
|
|
#define GCC_USB30_SLEEP_CLK 160
|
|
#define GCC_USB3_AUX_CLK 161
|
|
#define GCC_USB3_PIPE_CLK 162
|
|
#define GCC_USB_PHY_CFG_AHB_CLK 163
|
|
#define GCC_USB_SS_REF_CLK 164
|
|
#define GCC_VENUS0_AHB_CLK 165
|
|
#define GCC_VENUS0_AXI_CLK 166
|
|
#define GCC_VENUS0_CORE0_VCODEC0_CLK 167
|
|
#define GCC_VENUS0_VCODEC0_CLK 168
|
|
#define GCC_VENUS_TBU_CLK 169
|
|
#define GCC_VFE1_TBU_CLK 170
|
|
#define GCC_VFE_TBU_CLK 171
|
|
#define GFX3D_CLK_SRC 172
|
|
#define GP1_CLK_SRC 173
|
|
#define GP2_CLK_SRC 174
|
|
#define GP3_CLK_SRC 175
|
|
#define GPLL0 176
|
|
#define GPLL0_EARLY 177
|
|
#define GPLL2 178
|
|
#define GPLL2_EARLY 179
|
|
#define GPLL3 180
|
|
#define GPLL3_EARLY 181
|
|
#define GPLL4 182
|
|
#define GPLL4_EARLY 183
|
|
#define GPLL6 184
|
|
#define GPLL6_EARLY 185
|
|
#define JPEG0_CLK_SRC 186
|
|
#define MCLK0_CLK_SRC 187
|
|
#define MCLK1_CLK_SRC 188
|
|
#define MCLK2_CLK_SRC 189
|
|
#define MCLK3_CLK_SRC 190
|
|
#define MDP_CLK_SRC 191
|
|
#define PCLK0_CLK_SRC 192
|
|
#define PCLK1_CLK_SRC 193
|
|
#define PDM2_CLK_SRC 194
|
|
#define RBCPR_GFX_CLK_SRC 195
|
|
#define SDCC1_APPS_CLK_SRC 196
|
|
#define SDCC1_ICE_CORE_CLK_SRC 197
|
|
#define SDCC2_APPS_CLK_SRC 198
|
|
#define USB30_MASTER_CLK_SRC 199
|
|
#define USB30_MOCK_UTMI_CLK_SRC 200
|
|
#define USB3_AUX_CLK_SRC 201
|
|
#define VCODEC0_CLK_SRC 202
|
|
#define VFE0_CLK_SRC 203
|
|
#define VFE1_CLK_SRC 204
|
|
#define VSYNC_CLK_SRC 205
|
|
|
|
/* GCC block resets */
|
|
#define GCC_CAMSS_MICRO_BCR 0
|
|
#define GCC_MSS_BCR 1
|
|
#define GCC_QUSB2_PHY_BCR 2
|
|
#define GCC_USB3PHY_PHY_BCR 3
|
|
#define GCC_USB3_PHY_BCR 4
|
|
#define GCC_USB_30_BCR 5
|
|
#define GCC_MDSS_BCR 6
|
|
#define GCC_CRYPTO_BCR 7
|
|
#define GCC_SDCC1_BCR 8
|
|
#define GCC_SDCC2_BCR 9
|
|
|
|
/* GDSCs */
|
|
#define CPP_GDSC 0
|
|
#define JPEG_GDSC 1
|
|
#define MDSS_GDSC 2
|
|
#define OXILI_CX_GDSC 3
|
|
#define OXILI_GX_GDSC 4
|
|
#define USB30_GDSC 5
|
|
#define VENUS_CORE0_GDSC 6
|
|
#define VENUS_GDSC 7
|
|
#define VFE0_GDSC 8
|
|
#define VFE1_GDSC 9
|
|
|
|
#endif
|