249 lines
7.4 KiB
C
249 lines
7.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2021 Gerhard Engleder <gerhard@engleder-embedded.com> */
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/* Hardware definition of TSNEP and EtherCAT MAC device */
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#ifndef _TSNEP_HW_H
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#define _TSNEP_HW_H
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#include <linux/types.h>
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/* type */
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#define ECM_TYPE 0x0000
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#define ECM_REVISION_MASK 0x000000FF
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#define ECM_REVISION_SHIFT 0
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#define ECM_VERSION_MASK 0x0000FF00
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#define ECM_VERSION_SHIFT 8
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#define ECM_QUEUE_COUNT_MASK 0x00070000
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#define ECM_QUEUE_COUNT_SHIFT 16
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#define ECM_GATE_CONTROL 0x02000000
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/* system time */
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#define ECM_SYSTEM_TIME_LOW 0x0008
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#define ECM_SYSTEM_TIME_HIGH 0x000C
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/* clock */
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#define ECM_CLOCK_RATE 0x0010
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#define ECM_CLOCK_RATE_OFFSET_MASK 0x7FFFFFFF
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#define ECM_CLOCK_RATE_OFFSET_SIGN 0x80000000
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/* interrupt */
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#define ECM_INT_ENABLE 0x0018
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#define ECM_INT_ACTIVE 0x001C
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#define ECM_INT_ACKNOWLEDGE 0x001C
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#define ECM_INT_LINK 0x00000020
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#define ECM_INT_TX_0 0x00000100
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#define ECM_INT_RX_0 0x00000200
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#define ECM_INT_TXRX_SHIFT 2
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#define ECM_INT_ALL 0x7FFFFFFF
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#define ECM_INT_DISABLE 0x80000000
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/* reset */
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#define ECM_RESET 0x0020
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#define ECM_RESET_COMMON 0x00000001
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#define ECM_RESET_CHANNEL 0x00000100
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#define ECM_RESET_TXRX 0x00010000
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/* counter */
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#define ECM_COUNTER_LOW 0x0028
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#define ECM_COUNTER_HIGH 0x002C
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/* interrupt delay */
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#define ECM_INT_DELAY 0x0030
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#define ECM_INT_DELAY_MASK 0xF0
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#define ECM_INT_DELAY_SHIFT 4
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#define ECM_INT_DELAY_BASE_US 16
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#define ECM_INT_DELAY_OFFSET 1
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/* control and status */
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#define ECM_STATUS 0x0080
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#define ECM_LINK_MODE_OFF 0x01000000
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#define ECM_LINK_MODE_100 0x02000000
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#define ECM_LINK_MODE_1000 0x04000000
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#define ECM_NO_LINK 0x01000000
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#define ECM_LINK_MODE_MASK 0x06000000
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/* management data */
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#define ECM_MD_CONTROL 0x0084
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#define ECM_MD_STATUS 0x0084
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#define ECM_MD_PREAMBLE 0x00000001
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#define ECM_MD_READ 0x00000004
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#define ECM_MD_WRITE 0x00000002
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#define ECM_MD_ADDR_MASK 0x000000F8
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#define ECM_MD_ADDR_SHIFT 3
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#define ECM_MD_PHY_ADDR_MASK 0x00001F00
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#define ECM_MD_PHY_ADDR_SHIFT 8
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#define ECM_MD_BUSY 0x00000001
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#define ECM_MD_DATA_MASK 0xFFFF0000
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#define ECM_MD_DATA_SHIFT 16
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/* statistic */
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#define ECM_STAT 0x00B0
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#define ECM_STAT_RX_ERR_MASK 0x000000FF
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#define ECM_STAT_RX_ERR_SHIFT 0
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#define ECM_STAT_INV_FRM_MASK 0x0000FF00
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#define ECM_STAT_INV_FRM_SHIFT 8
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#define ECM_STAT_FWD_RX_ERR_MASK 0x00FF0000
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#define ECM_STAT_FWD_RX_ERR_SHIFT 16
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/* tsnep */
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#define TSNEP_MAC_SIZE 0x4000
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#define TSNEP_QUEUE_SIZE 0x1000
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#define TSNEP_QUEUE(n) ({ typeof(n) __n = (n); \
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(__n) == 0 ? \
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0 : \
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TSNEP_MAC_SIZE + TSNEP_QUEUE_SIZE * ((__n) - 1); })
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#define TSNEP_MAX_QUEUES 8
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#define TSNEP_MAX_FRAME_SIZE (2 * 1024) /* hardware supports actually 16k */
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#define TSNEP_DESC_SIZE 256
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#define TSNEP_DESC_OFFSET 128
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/* tsnep register */
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#define TSNEP_INFO 0x0100
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#define TSNEP_INFO_TX_TIME 0x00010000
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#define TSNEP_CONTROL 0x0108
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#define TSNEP_CONTROL_TX_RESET 0x00000001
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#define TSNEP_CONTROL_TX_ENABLE 0x00000002
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#define TSNEP_CONTROL_TX_DMA_ERROR 0x00000010
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#define TSNEP_CONTROL_TX_DESC_ERROR 0x00000020
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#define TSNEP_CONTROL_RX_RESET 0x00000100
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#define TSNEP_CONTROL_RX_ENABLE 0x00000200
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#define TSNEP_CONTROL_RX_DISABLE 0x00000400
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#define TSNEP_CONTROL_RX_DMA_ERROR 0x00001000
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#define TSNEP_CONTROL_RX_DESC_ERROR 0x00002000
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#define TSNEP_TX_DESC_ADDR_LOW 0x0140
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#define TSNEP_TX_DESC_ADDR_HIGH 0x0144
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#define TSNEP_RX_DESC_ADDR_LOW 0x0180
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#define TSNEP_RX_DESC_ADDR_HIGH 0x0184
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#define TSNEP_RESET_OWNER_COUNTER 0x01
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#define TSNEP_RX_STATISTIC 0x0190
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#define TSNEP_RX_STATISTIC_NO_DESC_MASK 0x000000FF
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#define TSNEP_RX_STATISTIC_NO_DESC_SHIFT 0
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#define TSNEP_RX_STATISTIC_BUFFER_TOO_SMALL_MASK 0x0000FF00
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#define TSNEP_RX_STATISTIC_BUFFER_TOO_SMALL_SHIFT 8
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#define TSNEP_RX_STATISTIC_FIFO_OVERFLOW_MASK 0x00FF0000
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#define TSNEP_RX_STATISTIC_FIFO_OVERFLOW_SHIFT 16
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#define TSNEP_RX_STATISTIC_INVALID_FRAME_MASK 0xFF000000
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#define TSNEP_RX_STATISTIC_INVALID_FRAME_SHIFT 24
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#define TSNEP_RX_STATISTIC_NO_DESC 0x0190
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#define TSNEP_RX_STATISTIC_BUFFER_TOO_SMALL 0x0191
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#define TSNEP_RX_STATISTIC_FIFO_OVERFLOW 0x0192
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#define TSNEP_RX_STATISTIC_INVALID_FRAME 0x0193
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#define TSNEP_MAC_ADDRESS_LOW 0x0800
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#define TSNEP_MAC_ADDRESS_HIGH 0x0804
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#define TSNEP_RX_FILTER 0x0806
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#define TSNEP_RX_FILTER_ACCEPT_ALL_MULTICASTS 0x0001
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#define TSNEP_RX_FILTER_ACCEPT_ALL_UNICASTS 0x0002
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#define TSNEP_GC 0x0808
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#define TSNEP_GC_ENABLE_A 0x00000002
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#define TSNEP_GC_ENABLE_B 0x00000004
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#define TSNEP_GC_DISABLE 0x00000008
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#define TSNEP_GC_ENABLE_TIMEOUT 0x00000010
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#define TSNEP_GC_ACTIVE_A 0x00000002
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#define TSNEP_GC_ACTIVE_B 0x00000004
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#define TSNEP_GC_CHANGE_AB 0x00000008
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#define TSNEP_GC_TIMEOUT_ACTIVE 0x00000010
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#define TSNEP_GC_TIMEOUT_SIGNAL 0x00000020
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#define TSNEP_GC_LIST_ERROR 0x00000080
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#define TSNEP_GC_OPEN 0x00FF0000
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#define TSNEP_GC_OPEN_SHIFT 16
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#define TSNEP_GC_NEXT_OPEN 0xFF000000
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#define TSNEP_GC_NEXT_OPEN_SHIFT 24
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#define TSNEP_GC_TIMEOUT 131072
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#define TSNEP_GC_TIME 0x080C
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#define TSNEP_GC_CHANGE 0x0810
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#define TSNEP_GCL_A 0x2000
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#define TSNEP_GCL_B 0x2800
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#define TSNEP_GCL_SIZE SZ_2K
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#define TSNEP_RX_ASSIGN 0x0840
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#define TSNEP_RX_ASSIGN_ACTIVE 0x00000001
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#define TSNEP_RX_ASSIGN_QUEUE_MASK 0x00000006
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#define TSNEP_RX_ASSIGN_QUEUE_SHIFT 1
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#define TSNEP_RX_ASSIGN_OFFSET 1
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#define TSNEP_RX_ASSIGN_ETHER_TYPE 0x0880
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#define TSNEP_RX_ASSIGN_ETHER_TYPE_OFFSET 2
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#define TSNEP_RX_ASSIGN_ETHER_TYPE_COUNT 2
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/* tsnep gate control list operation */
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struct tsnep_gcl_operation {
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u32 properties;
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u32 interval;
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};
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#define TSNEP_GCL_COUNT (TSNEP_GCL_SIZE / sizeof(struct tsnep_gcl_operation))
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#define TSNEP_GCL_MASK 0x000000FF
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#define TSNEP_GCL_INSERT 0x20000000
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#define TSNEP_GCL_CHANGE 0x40000000
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#define TSNEP_GCL_LAST 0x80000000
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#define TSNEP_GCL_MIN_INTERVAL 32
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/* tsnep TX/RX descriptor */
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#define TSNEP_DESC_SIZE 256
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#define TSNEP_DESC_SIZE_DATA_AFTER 2048
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#define TSNEP_DESC_OFFSET 128
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#define TSNEP_DESC_SIZE_DATA_AFTER_INLINE (64 - sizeof(struct tsnep_tx_desc) + \
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sizeof_field(struct tsnep_tx_desc, tx))
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#define TSNEP_DESC_OWNER_COUNTER_MASK 0xC0000000
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#define TSNEP_DESC_OWNER_COUNTER_SHIFT 30
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#define TSNEP_DESC_LENGTH_MASK 0x00003FFF
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#define TSNEP_DESC_INTERRUPT_FLAG 0x00040000
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#define TSNEP_DESC_EXTENDED_WRITEBACK_FLAG 0x00080000
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#define TSNEP_DESC_NO_LINK_FLAG 0x01000000
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/* tsnep TX descriptor */
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struct tsnep_tx_desc {
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__le32 properties;
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__le32 more_properties;
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__le32 reserved[2];
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__le64 next;
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__le64 tx;
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};
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#define TSNEP_TX_DESC_OWNER_MASK 0xE0000000
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#define TSNEP_TX_DESC_OWNER_USER_FLAG 0x20000000
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#define TSNEP_TX_DESC_LAST_FRAGMENT_FLAG 0x00010000
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#define TSNEP_TX_DESC_DATA_AFTER_DESC_FLAG 0x00020000
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/* tsnep TX descriptor writeback */
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struct tsnep_tx_desc_wb {
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__le32 properties;
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__le32 reserved1;
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__le64 counter;
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__le64 timestamp;
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__le32 dma_delay;
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__le32 reserved2;
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};
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#define TSNEP_TX_DESC_UNDERRUN_ERROR_FLAG 0x00010000
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#define TSNEP_TX_DESC_DMA_DELAY_FIRST_DATA_MASK 0x0000FFFC
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#define TSNEP_TX_DESC_DMA_DELAY_FIRST_DATA_SHIFT 2
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#define TSNEP_TX_DESC_DMA_DELAY_LAST_DATA_MASK 0xFFFC0000
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#define TSNEP_TX_DESC_DMA_DELAY_LAST_DATA_SHIFT 18
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#define TSNEP_TX_DESC_DMA_DELAY_NS 64
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/* tsnep RX descriptor */
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struct tsnep_rx_desc {
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__le32 properties;
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__le32 reserved[3];
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__le64 next;
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__le64 rx;
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};
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#define TSNEP_RX_DESC_BUFFER_SIZE_MASK 0x00003FFC
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/* tsnep RX descriptor writeback */
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struct tsnep_rx_desc_wb {
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__le32 properties;
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__le32 reserved[7];
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};
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/* tsnep RX inline meta */
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struct tsnep_rx_inline {
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__le64 counter;
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__le64 timestamp;
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};
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#define TSNEP_RX_INLINE_METADATA_SIZE (sizeof(struct tsnep_rx_inline))
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#endif /* _TSNEP_HW_H */
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