74 lines
2.7 KiB
YAML
74 lines
2.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: RISC-V Hart-Level Interrupt Controller (HLIC)
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description:
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RISC-V cores include Control Status Registers (CSRs) which are local to
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each CPU core (HART in RISC-V terminology) and can be read or written by
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software. Some of these CSRs are used to control local interrupts connected
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to the core. Every interrupt is ultimately routed through a hart's HLIC
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before it interrupts that hart.
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The RISC-V supervisor ISA manual specifies three interrupt sources that are
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attached to every HLIC namely software interrupts, the timer interrupt, and
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external interrupts. Software interrupts are used to send IPIs between
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cores. The timer interrupt comes from an architecturally mandated real-
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time timer that is controlled via Supervisor Binary Interface (SBI) calls
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and CSR reads. External interrupts connect all other device interrupts to
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the HLIC, which are routed via the platform-level interrupt controller
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(PLIC).
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All RISC-V systems that conform to the supervisor ISA specification are
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required to have a HLIC with these three interrupt sources present. Since
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the interrupt map is defined by the ISA it's not listed in the HLIC's device
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tree entry, though external interrupt controllers (like the PLIC, for
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example) will need to define how their interrupts map to the relevant HLICs.
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This means a PLIC interrupt property will typically list the HLICs for all
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present HARTs in the system.
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maintainers:
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- Palmer Dabbelt <palmer@dabbelt.com>
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- Paul Walmsley <paul.walmsley@sifive.com>
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properties:
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compatible:
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oneOf:
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- items:
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- const: andestech,cpu-intc
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- const: riscv,cpu-intc
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- const: riscv,cpu-intc
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interrupt-controller: true
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'#interrupt-cells':
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const: 1
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description: |
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The interrupt sources are defined by the RISC-V supervisor ISA manual,
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with only the following three interrupts being defined for
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supervisor mode:
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- Source 1 is the supervisor software interrupt, which can be sent by
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an SBI call and is reserved for use by software.
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- Source 5 is the supervisor timer interrupt, which can be configured
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by SBI calls and implements a one-shot timer.
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- Source 9 is the supervisor external interrupt, which chains to all
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other device interrupts.
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required:
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- compatible
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- '#interrupt-cells'
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- interrupt-controller
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additionalProperties: false
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examples:
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- |
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interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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