83 lines
2.5 KiB
C
83 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Exceptions for specific devices. Usually work-arounds for fatal design flaws.
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* Derived from fixup.c of i386 tree.
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*/
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/vgaarb.h>
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#include <linux/screen_info.h>
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#include <asm/machvec.h>
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/*
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* Fixup to mark boot BIOS video selected by BIOS before it changes
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*
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* From information provided by "Jon Smirl" <jonsmirl@gmail.com>
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*
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* The standard boot ROM sequence for an x86 machine uses the BIOS
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* to select an initial video card for boot display. This boot video
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* card will have its BIOS copied to 0xC0000 in system RAM.
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* IORESOURCE_ROM_SHADOW is used to associate the boot video
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* card with this copy. On laptops this copy has to be used since
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* the main ROM may be compressed or combined with another image.
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* See pci_map_rom() for use of this flag. Before marking the device
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* with IORESOURCE_ROM_SHADOW check if a vga_default_device is already set
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* by either arch code or vga-arbitration; if so only apply the fixup to this
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* already-determined primary video card.
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*/
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static void pci_fixup_video(struct pci_dev *pdev)
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{
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struct pci_dev *bridge;
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struct pci_bus *bus;
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u16 config;
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struct resource *res;
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if ((strcmp(ia64_platform_name, "dig") != 0)
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&& (strcmp(ia64_platform_name, "hpzx1") != 0))
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return;
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/* Maybe, this machine supports legacy memory map. */
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/* Is VGA routed to us? */
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bus = pdev->bus;
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while (bus) {
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bridge = bus->self;
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/*
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* From information provided by
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* "David Miller" <davem@davemloft.net>
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* The bridge control register is valid for PCI header
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* type BRIDGE, or CARDBUS. Host to PCI controllers use
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* PCI header type NORMAL.
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*/
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if (bridge && (pci_is_bridge(bridge))) {
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pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
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&config);
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if (!(config & PCI_BRIDGE_CTL_VGA))
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return;
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}
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bus = bus->parent;
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}
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if (!vga_default_device() || pdev == vga_default_device()) {
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pci_read_config_word(pdev, PCI_COMMAND, &config);
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if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
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res = &pdev->resource[PCI_ROM_RESOURCE];
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pci_disable_rom(pdev);
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if (res->parent)
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release_resource(res);
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res->start = 0xC0000;
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res->end = res->start + 0x20000 - 1;
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res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
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IORESOURCE_PCI_FIXED;
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dev_info(&pdev->dev, "Video device with shadowed ROM at %pR\n",
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res);
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}
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}
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}
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DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
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PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);
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