529 lines
12 KiB
C
529 lines
12 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2020-2021 Intel Corporation
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*/
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#include "gt/intel_migrate.h"
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#include "gt/intel_gpu_commands.h"
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#include "gem/i915_gem_ttm_move.h"
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#include "i915_deps.h"
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#include "selftests/igt_reset.h"
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#include "selftests/igt_spinner.h"
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static int igt_fill_check_buffer(struct drm_i915_gem_object *obj,
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bool fill)
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{
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struct drm_i915_private *i915 = to_i915(obj->base.dev);
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unsigned int i, count = obj->base.size / sizeof(u32);
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enum i915_map_type map_type =
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i915_coherent_map_type(i915, obj, false);
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u32 *cur;
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int err = 0;
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assert_object_held(obj);
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cur = i915_gem_object_pin_map(obj, map_type);
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if (IS_ERR(cur))
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return PTR_ERR(cur);
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if (fill)
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for (i = 0; i < count; ++i)
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*cur++ = i;
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else
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for (i = 0; i < count; ++i)
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if (*cur++ != i) {
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pr_err("Object content mismatch at location %d of %d\n", i, count);
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err = -EINVAL;
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break;
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}
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i915_gem_object_unpin_map(obj);
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return err;
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}
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static int igt_create_migrate(struct intel_gt *gt, enum intel_region_id src,
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enum intel_region_id dst)
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{
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struct drm_i915_private *i915 = gt->i915;
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struct intel_memory_region *src_mr = i915->mm.regions[src];
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struct intel_memory_region *dst_mr = i915->mm.regions[dst];
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struct drm_i915_gem_object *obj;
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struct i915_gem_ww_ctx ww;
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int err = 0;
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GEM_BUG_ON(!src_mr);
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GEM_BUG_ON(!dst_mr);
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/* Switch object backing-store on create */
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obj = i915_gem_object_create_region(src_mr, dst_mr->min_page_size, 0, 0);
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if (IS_ERR(obj))
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return PTR_ERR(obj);
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for_i915_gem_ww(&ww, err, true) {
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err = i915_gem_object_lock(obj, &ww);
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if (err)
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continue;
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err = igt_fill_check_buffer(obj, true);
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if (err)
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continue;
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err = i915_gem_object_migrate(obj, &ww, dst);
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if (err)
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continue;
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err = i915_gem_object_pin_pages(obj);
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if (err)
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continue;
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if (i915_gem_object_can_migrate(obj, src))
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err = -EINVAL;
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i915_gem_object_unpin_pages(obj);
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err = i915_gem_object_wait_migration(obj, true);
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if (err)
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continue;
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err = igt_fill_check_buffer(obj, false);
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}
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i915_gem_object_put(obj);
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return err;
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}
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static int igt_smem_create_migrate(void *arg)
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{
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return igt_create_migrate(arg, INTEL_REGION_LMEM_0, INTEL_REGION_SMEM);
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}
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static int igt_lmem_create_migrate(void *arg)
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{
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return igt_create_migrate(arg, INTEL_REGION_SMEM, INTEL_REGION_LMEM_0);
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}
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static int igt_same_create_migrate(void *arg)
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{
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return igt_create_migrate(arg, INTEL_REGION_LMEM_0, INTEL_REGION_LMEM_0);
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}
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static int lmem_pages_migrate_one(struct i915_gem_ww_ctx *ww,
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struct drm_i915_gem_object *obj,
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struct i915_vma *vma,
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bool silent_migrate)
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{
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int err;
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err = i915_gem_object_lock(obj, ww);
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if (err)
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return err;
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if (vma) {
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err = i915_vma_pin_ww(vma, ww, obj->base.size, 0,
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0UL | PIN_OFFSET_FIXED |
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PIN_USER);
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if (err) {
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if (err != -EINTR && err != ERESTARTSYS &&
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err != -EDEADLK)
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pr_err("Failed to pin vma.\n");
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return err;
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}
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i915_vma_unpin(vma);
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}
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/*
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* Migration will implicitly unbind (asynchronously) any bound
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* vmas.
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*/
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if (i915_gem_object_is_lmem(obj)) {
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err = i915_gem_object_migrate(obj, ww, INTEL_REGION_SMEM);
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if (err) {
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if (!silent_migrate)
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pr_err("Object failed migration to smem\n");
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if (err)
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return err;
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}
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if (i915_gem_object_is_lmem(obj)) {
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pr_err("object still backed by lmem\n");
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err = -EINVAL;
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}
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if (!i915_gem_object_has_struct_page(obj)) {
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pr_err("object not backed by struct page\n");
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err = -EINVAL;
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}
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} else {
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err = i915_gem_object_migrate(obj, ww, INTEL_REGION_LMEM_0);
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if (err) {
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if (!silent_migrate)
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pr_err("Object failed migration to lmem\n");
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if (err)
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return err;
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}
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if (i915_gem_object_has_struct_page(obj)) {
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pr_err("object still backed by struct page\n");
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err = -EINVAL;
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}
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if (!i915_gem_object_is_lmem(obj)) {
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pr_err("object not backed by lmem\n");
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err = -EINVAL;
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}
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}
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return err;
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}
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static int __igt_lmem_pages_migrate(struct intel_gt *gt,
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struct i915_address_space *vm,
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struct i915_deps *deps,
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struct igt_spinner *spin,
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struct dma_fence *spin_fence,
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bool borked_migrate)
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{
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struct drm_i915_private *i915 = gt->i915;
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma = NULL;
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struct i915_gem_ww_ctx ww;
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struct i915_request *rq;
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int err;
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int i;
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/* From LMEM to shmem and back again */
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obj = i915_gem_object_create_lmem(i915, SZ_2M, 0);
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if (IS_ERR(obj))
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return PTR_ERR(obj);
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if (vm) {
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vma = i915_vma_instance(obj, vm, NULL);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto out_put;
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}
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}
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/* Initial GPU fill, sync, CPU initialization. */
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for_i915_gem_ww(&ww, err, true) {
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err = i915_gem_object_lock(obj, &ww);
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if (err)
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continue;
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err = ____i915_gem_object_get_pages(obj);
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if (err)
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continue;
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err = intel_migrate_clear(>->migrate, &ww, deps,
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obj->mm.pages->sgl, obj->cache_level,
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i915_gem_object_is_lmem(obj),
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0xdeadbeaf, &rq);
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if (rq) {
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err = dma_resv_reserve_fences(obj->base.resv, 1);
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if (!err)
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dma_resv_add_fence(obj->base.resv, &rq->fence,
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DMA_RESV_USAGE_KERNEL);
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i915_request_put(rq);
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}
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if (err)
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continue;
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if (!vma) {
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err = igt_fill_check_buffer(obj, true);
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if (err)
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continue;
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}
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}
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if (err)
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goto out_put;
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/*
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* Migrate to and from smem without explicitly syncing.
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* Finalize with data in smem for fast readout.
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*/
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for (i = 1; i <= 5; ++i) {
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for_i915_gem_ww(&ww, err, true)
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err = lmem_pages_migrate_one(&ww, obj, vma,
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borked_migrate);
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if (err)
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goto out_put;
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}
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err = i915_gem_object_lock_interruptible(obj, NULL);
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if (err)
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goto out_put;
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if (spin) {
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if (dma_fence_is_signaled(spin_fence)) {
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pr_err("Spinner was terminated by hangcheck.\n");
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err = -EBUSY;
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goto out_unlock;
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}
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igt_spinner_end(spin);
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}
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/* Finally sync migration and check content. */
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err = i915_gem_object_wait_migration(obj, true);
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if (err)
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goto out_unlock;
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if (vma) {
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err = i915_vma_wait_for_bind(vma);
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if (err)
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goto out_unlock;
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} else {
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err = igt_fill_check_buffer(obj, false);
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}
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out_unlock:
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i915_gem_object_unlock(obj);
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out_put:
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i915_gem_object_put(obj);
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return err;
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}
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static int igt_lmem_pages_failsafe_migrate(void *arg)
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{
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int fail_gpu, fail_alloc, ban_memcpy, ret;
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struct intel_gt *gt = arg;
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for (fail_gpu = 0; fail_gpu < 2; ++fail_gpu) {
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for (fail_alloc = 0; fail_alloc < 2; ++fail_alloc) {
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for (ban_memcpy = 0; ban_memcpy < 2; ++ban_memcpy) {
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pr_info("Simulated failure modes: gpu: %d, alloc:%d, ban_memcpy: %d\n",
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fail_gpu, fail_alloc, ban_memcpy);
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i915_ttm_migrate_set_ban_memcpy(ban_memcpy);
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i915_ttm_migrate_set_failure_modes(fail_gpu,
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fail_alloc);
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ret = __igt_lmem_pages_migrate(gt, NULL, NULL,
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NULL, NULL,
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ban_memcpy &&
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fail_gpu);
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if (ban_memcpy && fail_gpu) {
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struct intel_gt *__gt;
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unsigned int id;
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if (ret != -EIO) {
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pr_err("expected -EIO, got (%d)\n", ret);
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ret = -EINVAL;
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} else {
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ret = 0;
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}
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for_each_gt(__gt, gt->i915, id) {
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intel_wakeref_t wakeref;
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bool wedged;
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mutex_lock(&__gt->reset.mutex);
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wedged = test_bit(I915_WEDGED, &__gt->reset.flags);
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mutex_unlock(&__gt->reset.mutex);
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if (fail_gpu && !fail_alloc) {
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if (!wedged) {
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pr_err("gt(%u) not wedged\n", id);
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ret = -EINVAL;
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continue;
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}
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} else if (wedged) {
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pr_err("gt(%u) incorrectly wedged\n", id);
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ret = -EINVAL;
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} else {
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continue;
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}
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wakeref = intel_runtime_pm_get(__gt->uncore->rpm);
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igt_global_reset_lock(__gt);
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intel_gt_reset(__gt, ALL_ENGINES, NULL);
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igt_global_reset_unlock(__gt);
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intel_runtime_pm_put(__gt->uncore->rpm, wakeref);
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}
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if (ret)
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goto out_err;
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}
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}
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}
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}
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out_err:
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i915_ttm_migrate_set_failure_modes(false, false);
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i915_ttm_migrate_set_ban_memcpy(false);
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return ret;
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}
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/*
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* This subtest tests that unbinding at migration is indeed performed
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* async. We launch a spinner and a number of migrations depending on
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* that spinner to have terminated. Before each migration we bind a
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* vma, which should then be async unbound by the migration operation.
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* If we are able to schedule migrations without blocking while the
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* spinner is still running, those unbinds are indeed async and non-
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* blocking.
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*
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* Note that each async bind operation is awaiting the previous migration
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* due to the moving fence resulting from the migration.
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*/
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static int igt_async_migrate(struct intel_gt *gt)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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struct i915_ppgtt *ppgtt;
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struct igt_spinner spin;
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int err;
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ppgtt = i915_ppgtt_create(gt, 0);
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if (IS_ERR(ppgtt))
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return PTR_ERR(ppgtt);
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if (igt_spinner_init(&spin, gt)) {
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err = -ENOMEM;
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goto out_spin;
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}
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for_each_engine(engine, gt, id) {
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struct ttm_operation_ctx ctx = {
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.interruptible = true
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};
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struct dma_fence *spin_fence;
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struct intel_context *ce;
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struct i915_request *rq;
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struct i915_deps deps;
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ce = intel_context_create(engine);
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if (IS_ERR(ce)) {
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err = PTR_ERR(ce);
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goto out_ce;
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}
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/*
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* Use MI_NOOP, making the spinner non-preemptible. If there
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* is a code path where we fail async operation due to the
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* running spinner, we will block and fail to end the
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* spinner resulting in a deadlock. But with a non-
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* preemptible spinner, hangcheck will terminate the spinner
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* for us, and we will later detect that and fail the test.
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*/
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rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
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intel_context_put(ce);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto out_ce;
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}
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i915_deps_init(&deps, GFP_KERNEL);
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err = i915_deps_add_dependency(&deps, &rq->fence, &ctx);
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spin_fence = dma_fence_get(&rq->fence);
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i915_request_add(rq);
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if (err)
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goto out_ce;
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err = __igt_lmem_pages_migrate(gt, &ppgtt->vm, &deps, &spin,
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spin_fence, false);
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i915_deps_fini(&deps);
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dma_fence_put(spin_fence);
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if (err)
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goto out_ce;
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}
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out_ce:
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igt_spinner_fini(&spin);
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out_spin:
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i915_vm_put(&ppgtt->vm);
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return err;
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}
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/*
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* Setting ASYNC_FAIL_ALLOC to 2 will simulate memory allocation failure while
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* arming the migration error check and block async migration. This
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* will cause us to deadlock and hangcheck will terminate the spinner
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* causing the test to fail.
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*/
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#define ASYNC_FAIL_ALLOC 1
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static int igt_lmem_async_migrate(void *arg)
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{
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int fail_gpu, fail_alloc, ban_memcpy, ret;
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struct intel_gt *gt = arg;
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for (fail_gpu = 0; fail_gpu < 2; ++fail_gpu) {
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for (fail_alloc = 0; fail_alloc < ASYNC_FAIL_ALLOC; ++fail_alloc) {
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for (ban_memcpy = 0; ban_memcpy < 2; ++ban_memcpy) {
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pr_info("Simulated failure modes: gpu: %d, alloc: %d, ban_memcpy: %d\n",
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fail_gpu, fail_alloc, ban_memcpy);
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i915_ttm_migrate_set_ban_memcpy(ban_memcpy);
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i915_ttm_migrate_set_failure_modes(fail_gpu,
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fail_alloc);
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ret = igt_async_migrate(gt);
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if (fail_gpu && ban_memcpy) {
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struct intel_gt *__gt;
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unsigned int id;
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if (ret != -EIO) {
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pr_err("expected -EIO, got (%d)\n", ret);
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ret = -EINVAL;
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} else {
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ret = 0;
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}
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for_each_gt(__gt, gt->i915, id) {
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intel_wakeref_t wakeref;
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bool wedged;
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mutex_lock(&__gt->reset.mutex);
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wedged = test_bit(I915_WEDGED, &__gt->reset.flags);
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mutex_unlock(&__gt->reset.mutex);
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if (fail_gpu && !fail_alloc) {
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if (!wedged) {
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pr_err("gt(%u) not wedged\n", id);
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ret = -EINVAL;
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continue;
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}
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} else if (wedged) {
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pr_err("gt(%u) incorrectly wedged\n", id);
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ret = -EINVAL;
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} else {
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continue;
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}
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wakeref = intel_runtime_pm_get(__gt->uncore->rpm);
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igt_global_reset_lock(__gt);
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intel_gt_reset(__gt, ALL_ENGINES, NULL);
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igt_global_reset_unlock(__gt);
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intel_runtime_pm_put(__gt->uncore->rpm, wakeref);
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}
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}
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if (ret)
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goto out_err;
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}
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}
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}
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out_err:
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i915_ttm_migrate_set_failure_modes(false, false);
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i915_ttm_migrate_set_ban_memcpy(false);
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return ret;
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}
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int i915_gem_migrate_live_selftests(struct drm_i915_private *i915)
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{
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static const struct i915_subtest tests[] = {
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SUBTEST(igt_smem_create_migrate),
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SUBTEST(igt_lmem_create_migrate),
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SUBTEST(igt_same_create_migrate),
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SUBTEST(igt_lmem_pages_failsafe_migrate),
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SUBTEST(igt_lmem_async_migrate),
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|
};
|
|
|
|
if (!HAS_LMEM(i915))
|
|
return 0;
|
|
|
|
return intel_gt_live_subtests(tests, to_gt(i915));
|
|
}
|