156 lines
5.0 KiB
C
156 lines
5.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2022 Intel Corporation
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*/
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#ifndef __IPC4_FW_REG_H__
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#define __IPC4_FW_REG_H__
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#define SOF_IPC4_INVALID_STREAM_POSITION ULLONG_MAX
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/**
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* struct sof_ipc4_pipeline_registers - Pipeline start and end information in fw
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* @stream_start_offset: Stream start offset (LPIB) reported by mixin
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* module allocated on pipeline attached to Host Output Gateway when
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* first data is being mixed to mixout module. When data is not mixed
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* (right after creation/after reset) value "(u64)-1" is reported
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* @stream_end_offset: Stream end offset (LPIB) reported by mixin
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* module allocated on pipeline attached to Host Output Gateway
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* during transition from RUNNING to PAUSED. When data is not mixed
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* (right after creation or after reset) value "(u64)-1" is reported.
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* When first data is mixed then value "0"is reported.
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*/
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struct sof_ipc4_pipeline_registers {
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u64 stream_start_offset;
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u64 stream_end_offset;
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} __packed __aligned(4);
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#define SOF_IPC4_PV_MAX_SUPPORTED_CHANNELS 8
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/**
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* struct sof_ipc4_peak_volume_regs - Volume information in fw
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* @peak_meter: Peak volume value in fw
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* @current_volume: Current volume value in fw
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* @target_volume: Target volume value in fw
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*/
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struct sof_ipc4_peak_volume_regs {
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u32 peak_meter[SOF_IPC4_PV_MAX_SUPPORTED_CHANNELS];
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u32 current_volume[SOF_IPC4_PV_MAX_SUPPORTED_CHANNELS];
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u32 target_volume[SOF_IPC4_PV_MAX_SUPPORTED_CHANNELS];
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} __packed __aligned(4);
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/**
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* struct sof_ipc4_llp_reading - Llp information in fw
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* @llp_l: Lower part of 64-bit LLP
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* @llp_u: Upper part of 64-bit LLP
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* @wclk_l: Lower part of 64-bit Wallclock
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* @wclk_u: Upper part of 64-bit Wallclock
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*/
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struct sof_ipc4_llp_reading {
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u32 llp_l;
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u32 llp_u;
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u32 wclk_l;
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u32 wclk_u;
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} __packed __aligned(4);
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/**
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* struct of sof_ipc4_llp_reading_extended - Extended llp info
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* @llp_reading: Llp information in memory window
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* @tpd_low: Total processed data (low part)
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* @tpd_high: Total processed data (high part)
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*/
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struct sof_ipc4_llp_reading_extended {
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struct sof_ipc4_llp_reading llp_reading;
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u32 tpd_low;
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u32 tpd_high;
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} __packed __aligned(4);
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/**
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* struct sof_ipc4_llp_reading_slot - Llp slot information in memory window
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* @node_id: Dai gateway node id
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* @reading: Llp information in memory window
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*/
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struct sof_ipc4_llp_reading_slot {
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u32 node_id;
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struct sof_ipc4_llp_reading reading;
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} __packed __aligned(4);
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/* ROM information */
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#define SOF_IPC4_FW_FUSE_VALUE_MASK GENMASK(7, 0)
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#define SOF_IPC4_FW_LOAD_METHOD_MASK BIT(8)
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#define SOF_IPC4_FW_DOWNLINK_IPC_USE_DMA_MASK BIT(9)
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#define SOF_IPC4_FW_LOAD_METHOD_REV_MASK GENMASK(11, 10)
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#define SOF_IPC4_FW_REVISION_MIN_MASK GENMASK(15, 12)
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#define SOF_IPC4_FW_REVISION_MAJ_MASK GENMASK(19, 16)
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#define SOF_IPC4_FW_VERSION_MIN_MASK GENMASK(23, 20)
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#define SOF_IPC4_FW_VERSION_MAJ_MASK GENMASK(27, 24)
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/* Number of dsp core supported in FW Regs. */
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#define SOF_IPC4_MAX_SUPPORTED_ADSP_CORES 8
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/* Number of host pipeline registers slots in FW Regs. */
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#define SOF_IPC4_MAX_PIPELINE_REG_SLOTS 16
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/* Number of PeakVol registers slots in FW Regs. */
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#define SOF_IPC4_MAX_PEAK_VOL_REG_SLOTS 16
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/* Number of GPDMA LLP Reading slots in FW Regs. */
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#define SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS 24
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/* Number of Aggregated SNDW Reading slots in FW Regs. */
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#define SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS 15
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/* Current ABI version of the Fw registers layout. */
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#define SOF_IPC4_FW_REGS_ABI_VER 1
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/**
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* struct sof_ipc4_fw_registers - FW Registers exposes additional
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* DSP / FW state information to the driver
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* @fw_status: Current ROM / FW status
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* @lec: Last ROM / FW error code
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* @fps: Current DSP clock status
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* @lnec: Last Native Error Code(from external library)
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* @ltr: Copy of LTRC HW register value(FW only)
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* @rsvd0: Reserved0
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* @rom_info: ROM info
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* @abi_ver: Version of the layout, set to the current FW_REGS_ABI_VER
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* @slave_core_sts: Slave core states
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* @rsvd2: Reserved2
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* @pipeline_regs: State of pipelines attached to host output gateways
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* @peak_vol_regs: State of PeakVol instances indexed by the PeakVol's instance_id
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* @llp_gpdma_reading_slots: LLP Readings for single link gateways
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* @llp_sndw_reading_slots: SNDW aggregated link gateways
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* @llp_evad_reading_slot: LLP Readings for EVAD gateway
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*/
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struct sof_ipc4_fw_registers {
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u32 fw_status;
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u32 lec;
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u32 fps;
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u32 lnec;
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u32 ltr;
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u32 rsvd0;
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u32 rom_info;
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u32 abi_ver;
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u8 slave_core_sts[SOF_IPC4_MAX_SUPPORTED_ADSP_CORES];
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u32 rsvd2[6];
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struct sof_ipc4_pipeline_registers
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pipeline_regs[SOF_IPC4_MAX_PIPELINE_REG_SLOTS];
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struct sof_ipc4_peak_volume_regs
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peak_vol_regs[SOF_IPC4_MAX_PEAK_VOL_REG_SLOTS];
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struct sof_ipc4_llp_reading_slot
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llp_gpdma_reading_slots[SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS];
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struct sof_ipc4_llp_reading_slot
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llp_sndw_reading_slots[SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS];
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struct sof_ipc4_llp_reading_slot llp_evad_reading_slot;
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} __packed __aligned(4);
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#endif
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