78 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			78 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* SPDX-License-Identifier: GPL-2.0 */
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| /*
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|  * Copyright (c) 2019 MediaTek Inc.
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|  */
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| 
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| #ifndef __SND_SOC_MT6660_H
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| #define __SND_SOC_MT6660_H
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| 
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| #include <linux/mutex.h>
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| #include <linux/regmap.h>
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| 
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| #pragma pack(push, 1)
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| struct mt6660_platform_data {
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| 	u8 init_setting_num;
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| 	u32 *init_setting_addr;
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| 	u32 *init_setting_mask;
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| 	u32 *init_setting_val;
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| };
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| 
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| struct mt6660_chip {
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| 	struct i2c_client *i2c;
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| 	struct device *dev;
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| 	struct platform_device *param_dev;
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| 	struct mt6660_platform_data plat_data;
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| 	struct mutex io_lock;
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| 	struct regmap *regmap;
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| 	u16 chip_rev;
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| };
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| #pragma pack(pop)
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| 
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| #define MT6660_REG_DEVID		(0x00)
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| #define MT6660_REG_SYSTEM_CTRL		(0x03)
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| #define MT6660_REG_IRQ_STATUS1		(0x05)
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| #define MT6660_REG_ADDA_CLOCK		(0x07)
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| #define MT6660_REG_SERIAL_CFG1		(0x10)
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| #define MT6660_REG_DATAO_SEL		(0x12)
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| #define MT6660_REG_TDM_CFG3		(0x15)
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| #define MT6660_REG_HPF_CTRL		(0x18)
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| #define MT6660_REG_HPF1_COEF		(0x1A)
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| #define MT6660_REG_HPF2_COEF		(0x1B)
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| #define MT6660_REG_PATH_BYPASS		(0x1E)
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| #define MT6660_REG_WDT_CTRL		(0x20)
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| #define MT6660_REG_HCLIP_CTRL		(0x24)
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| #define MT6660_REG_VOL_CTRL		(0x29)
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| #define MT6660_REG_SPS_CTRL		(0x30)
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| #define MT6660_REG_SIGMAX		(0x33)
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| #define MT6660_REG_CALI_T0		(0x3F)
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| #define MT6660_REG_BST_CTRL		(0x40)
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| #define MT6660_REG_PROTECTION_CFG	(0x46)
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| #define MT6660_REG_DA_GAIN		(0x4c)
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| #define MT6660_REG_AUDIO_IN2_SEL	(0x50)
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| #define MT6660_REG_SIG_GAIN		(0x51)
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| #define MT6660_REG_PLL_CFG1		(0x60)
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| #define MT6660_REG_DRE_CTRL		(0x68)
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| #define MT6660_REG_DRE_THDMODE		(0x69)
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| #define MT6660_REG_DRE_CORASE		(0x6B)
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| #define MT6660_REG_PWM_CTRL		(0x70)
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| #define MT6660_REG_DC_PROTECT_CTRL	(0x74)
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| #define MT6660_REG_ADC_USB_MODE		(0x7c)
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| #define MT6660_REG_INTERNAL_CFG		(0x88)
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| #define MT6660_REG_RESV0		(0x98)
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| #define MT6660_REG_RESV1		(0x99)
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| #define MT6660_REG_RESV2		(0x9A)
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| #define MT6660_REG_RESV3		(0x9B)
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| #define MT6660_REG_RESV6		(0xA2)
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| #define MT6660_REG_RESV7		(0xA3)
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| #define MT6660_REG_RESV10		(0xB0)
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| #define MT6660_REG_RESV11		(0xB1)
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| #define MT6660_REG_RESV16		(0xB6)
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| #define MT6660_REG_RESV17		(0xB7)
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| #define MT6660_REG_RESV19		(0xB9)
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| #define MT6660_REG_RESV21		(0xBB)
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| #define MT6660_REG_RESV23		(0xBD)
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| #define MT6660_REG_RESV31		(0xD3)
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| #define MT6660_REG_RESV40		(0xE0)
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| 
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| #endif /* __SND_SOC_MT6660_H */
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