515 lines
16 KiB
C
515 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* cs35l45.h - CS35L45 ALSA SoC audio driver
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*
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* Copyright 2019-2022 Cirrus Logic, Inc.
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*
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* Author: James Schulman <james.schulman@cirrus.com>
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*
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*/
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#ifndef CS35L45_H
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#define CS35L45_H
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <dt-bindings/sound/cs35l45.h>
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#include "wm_adsp.h"
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#define CS35L45_DEVID 0x00000000
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#define CS35L45_REVID 0x00000004
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#define CS35L45_RELID 0x0000000C
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#define CS35L45_OTPID 0x00000010
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#define CS35L45_SFT_RESET 0x00000020
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#define CS35L45_GLOBAL_ENABLES 0x00002014
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#define CS35L45_BLOCK_ENABLES 0x00002018
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#define CS35L45_BLOCK_ENABLES2 0x0000201C
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#define CS35L45_ERROR_RELEASE 0x00002034
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#define CS35L45_SYNC_GPIO1 0x00002430
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#define CS35L45_INTB_GPIO2_MCLK_REF 0x00002434
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#define CS35L45_GPIO3 0x00002438
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#define CS35L45_PWRMGT_CTL 0x00002900
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#define CS35L45_WAKESRC_CTL 0x00002904
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#define CS35L45_WKI2C_CTL 0x00002908
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#define CS35L45_PWRMGT_STS 0x0000290C
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#define CS35L45_REFCLK_INPUT 0x00002C04
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#define CS35L45_GLOBAL_SAMPLE_RATE 0x00002C0C
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#define CS35L45_BOOST_CCM_CFG 0x00003808
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#define CS35L45_BOOST_DCM_CFG 0x0000380C
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#define CS35L45_BOOST_OV_CFG 0x0000382C
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#define CS35L45_ASP_ENABLES1 0x00004800
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#define CS35L45_ASP_CONTROL1 0x00004804
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#define CS35L45_ASP_CONTROL2 0x00004808
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#define CS35L45_ASP_CONTROL3 0x0000480C
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#define CS35L45_ASP_FRAME_CONTROL1 0x00004810
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#define CS35L45_ASP_FRAME_CONTROL2 0x00004814
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#define CS35L45_ASP_FRAME_CONTROL5 0x00004820
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#define CS35L45_ASP_DATA_CONTROL1 0x00004830
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#define CS35L45_ASP_DATA_CONTROL5 0x00004840
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#define CS35L45_DACPCM1_INPUT 0x00004C00
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#define CS35L45_ASPTX1_INPUT 0x00004C20
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#define CS35L45_ASPTX2_INPUT 0x00004C24
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#define CS35L45_ASPTX3_INPUT 0x00004C28
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#define CS35L45_ASPTX4_INPUT 0x00004C2C
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#define CS35L45_ASPTX5_INPUT 0x00004C30
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#define CS35L45_DSP1RX1_INPUT 0x00004C40
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#define CS35L45_DSP1RX2_INPUT 0x00004C44
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#define CS35L45_DSP1RX3_INPUT 0x00004C48
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#define CS35L45_DSP1RX4_INPUT 0x00004C4C
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#define CS35L45_DSP1RX5_INPUT 0x00004C50
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#define CS35L45_DSP1RX6_INPUT 0x00004C54
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#define CS35L45_DSP1RX7_INPUT 0x00004C58
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#define CS35L45_DSP1RX8_INPUT 0x00004C5C
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#define CS35L45_HVLV_CONFIG 0x00006400
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#define CS35L45_LDPM_CONFIG 0x00006404
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#define CS35L45_AMP_PCM_CONTROL 0x00007000
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#define CS35L45_AMP_PCM_HPF_TST 0x00007004
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#define CS35L45_AMP_GAIN 0x00007800
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#define CS35L45_IRQ1_CFG 0x0000E000
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#define CS35L45_IRQ1_STATUS 0x0000E004
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#define CS35L45_IRQ1_EINT_1 0x0000E010
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#define CS35L45_IRQ1_EINT_2 0x0000E014
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#define CS35L45_IRQ1_EINT_3 0x0000E018
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#define CS35L45_IRQ1_EINT_4 0x0000E01C
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#define CS35L45_IRQ1_EINT_5 0x0000E020
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#define CS35L45_IRQ1_EINT_7 0x0000E028
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#define CS35L45_IRQ1_EINT_8 0x0000E02C
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#define CS35L45_IRQ1_EINT_18 0x0000E054
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#define CS35L45_IRQ1_STS_1 0x0000E090
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#define CS35L45_IRQ1_STS_2 0x0000E094
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#define CS35L45_IRQ1_STS_3 0x0000E098
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#define CS35L45_IRQ1_STS_4 0x0000E09C
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#define CS35L45_IRQ1_STS_5 0x0000E0A0
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#define CS35L45_IRQ1_STS_7 0x0000E0A8
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#define CS35L45_IRQ1_STS_8 0x0000E0AC
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#define CS35L45_IRQ1_STS_18 0x0000E0D4
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#define CS35L45_IRQ1_MASK_1 0x0000E110
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#define CS35L45_IRQ1_MASK_2 0x0000E114
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#define CS35L45_IRQ1_MASK_3 0x0000E118
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#define CS35L45_IRQ1_MASK_4 0x0000E11C
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#define CS35L45_IRQ1_MASK_5 0x0000E120
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#define CS35L45_IRQ1_MASK_6 0x0000E124
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#define CS35L45_IRQ1_MASK_7 0x0000E128
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#define CS35L45_IRQ1_MASK_8 0x0000E12C
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#define CS35L45_IRQ1_MASK_9 0x0000E130
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#define CS35L45_IRQ1_MASK_10 0x0000E134
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#define CS35L45_IRQ1_MASK_11 0x0000E138
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#define CS35L45_IRQ1_MASK_12 0x0000E13C
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#define CS35L45_IRQ1_MASK_13 0x0000E140
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#define CS35L45_IRQ1_MASK_14 0x0000E144
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#define CS35L45_IRQ1_MASK_15 0x0000E148
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#define CS35L45_IRQ1_MASK_16 0x0000E14C
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#define CS35L45_IRQ1_MASK_17 0x0000E150
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#define CS35L45_IRQ1_MASK_18 0x0000E154
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#define CS35L45_GPIO_STATUS1 0x0000F000
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#define CS35L45_GPIO1_CTRL1 0x0000F008
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#define CS35L45_GPIO2_CTRL1 0x0000F00C
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#define CS35L45_GPIO3_CTRL1 0x0000F010
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#define CS35L45_DSP_MBOX_1 0x00011000
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#define CS35L45_DSP_MBOX_2 0x00011004
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#define CS35L45_DSP_VIRT1_MBOX_1 0x00011020
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#define CS35L45_DSP_VIRT1_MBOX_2 0x00011024
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#define CS35L45_DSP_VIRT1_MBOX_3 0x00011028
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#define CS35L45_DSP_VIRT1_MBOX_4 0x0001102C
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#define CS35L45_DSP_VIRT2_MBOX_1 0x00011040
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#define CS35L45_DSP_VIRT2_MBOX_2 0x00011044
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#define CS35L45_DSP_VIRT2_MBOX_3 0x00011048
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#define CS35L45_DSP_VIRT2_MBOX_4 0x0001104C
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#define CS35L45_DSP1_XMEM_PACK_0 0x02000000
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#define CS35L45_DSP1_XMEM_PACK_4607 0x020047FC
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#define CS35L45_DSP1_XMEM_UNPACK32_0 0x02400000
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#define CS35L45_DSP1_XMEM_UNPACK32_3071 0x02402FFC
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#define CS35L45_DSP1_SYS_ID 0x025E0000
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#define CS35L45_DSP1_XMEM_UNPACK24_0 0x02800000
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#define CS35L45_DSP1_XMEM_UNPACK24_6143 0x02805FFC
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#define CS35L45_DSP1_CLOCK_FREQ 0x02B80000
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#define CS35L45_DSP1_RX1_RATE 0x02B80080
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#define CS35L45_DSP1_RX2_RATE 0x02B80088
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#define CS35L45_DSP1_RX3_RATE 0x02B80090
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#define CS35L45_DSP1_RX4_RATE 0x02B80098
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#define CS35L45_DSP1_RX5_RATE 0x02B800A0
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#define CS35L45_DSP1_RX6_RATE 0x02B800A8
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#define CS35L45_DSP1_RX7_RATE 0x02B800B0
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#define CS35L45_DSP1_RX8_RATE 0x02B800B8
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#define CS35L45_DSP1_TX1_RATE 0x02B80280
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#define CS35L45_DSP1_TX2_RATE 0x02B80288
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#define CS35L45_DSP1_TX3_RATE 0x02B80290
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#define CS35L45_DSP1_TX4_RATE 0x02B80298
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#define CS35L45_DSP1_TX5_RATE 0x02B802A0
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#define CS35L45_DSP1_TX6_RATE 0x02B802A8
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#define CS35L45_DSP1_TX7_RATE 0x02B802B0
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#define CS35L45_DSP1_TX8_RATE 0x02B802B8
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#define CS35L45_DSP1_SCRATCH1 0x02B805C0
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#define CS35L45_DSP1_SCRATCH2 0x02B805C8
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#define CS35L45_DSP1_SCRATCH3 0x02B805D0
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#define CS35L45_DSP1_SCRATCH4 0x02B805D8
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#define CS35L45_DSP1_CCM_CORE_CONTROL 0x02BC1000
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#define CS35L45_DSP1_YMEM_PACK_0 0x02C00000
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#define CS35L45_DSP1_YMEM_PACK_1532 0x02C017F0
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#define CS35L45_DSP1_YMEM_UNPACK32_0 0x03000000
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#define CS35L45_DSP1_YMEM_UNPACK32_1022 0x03000FF8
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#define CS35L45_DSP1_YMEM_UNPACK24_0 0x03400000
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#define CS35L45_DSP1_YMEM_UNPACK24_2043 0x03401FEC
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#define CS35L45_DSP1_PMEM_0 0x03800000
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#define CS35L45_DSP1_PMEM_3834 0x03803BE8
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#define CS35L45_LASTREG 0x03C6EFE8
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/* SFT_RESET */
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#define CS35L45_SOFT_RESET_TRIGGER 0x5A000000
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/* GLOBAL_ENABLES */
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#define CS35L45_GLOBAL_EN_SHIFT 0
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#define CS35L45_GLOBAL_EN_MASK BIT(0)
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/* BLOCK_ENABLES */
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#define CS35L45_IMON_EN_SHIFT 13
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#define CS35L45_VMON_EN_SHIFT 12
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#define CS35L45_TEMPMON_EN_SHIFT 10
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#define CS35L45_VDD_BSTMON_EN_SHIFT 9
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#define CS35L45_VDD_BATTMON_EN_SHIFT 8
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#define CS35L45_BST_EN_SHIFT 4
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#define CS35L45_BST_EN_MASK GENMASK(5, 4)
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#define CS35L45_RCV_EN_SHIFT 2
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#define CS35L45_RCV_EN_MASK BIT(2)
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#define CS35L45_AMP_EN_SHIFT 0
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#define CS35L45_AMP_EN_MASK BIT(0)
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#define CS35L45_BST_DISABLE_FET_OFF 0x00
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#define CS35L45_BST_DISABLE_FET_ON 0x01
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#define CS35L45_BST_ENABLE 0x02
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/* BLOCK_ENABLES2 */
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#define CS35L45_ASP_EN_SHIFT 27
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#define CS35L45_AMP_DRE_EN_SHIFT 20
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#define CS35L45_AMP_DRE_EN_MASK BIT(20)
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#define CS35L45_MEM_RDY_SHIFT 1
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#define CS35L45_MEM_RDY_MASK BIT(1)
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/* ERROR_RELEASE */
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#define CS35L45_GLOBAL_ERR_RLS_MASK BIT(11)
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/* CCM_CORE */
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#define CS35L45_CCM_CORE_RESET_SHIFT 9
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#define CS35L45_CCM_CORE_RESET_MASK BIT(9)
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#define CS35L45_CCM_PM_REMAP_SHIFT 7
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#define CS35L45_CCM_PM_REMAP_MASK BIT(7)
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#define CS35L45_CCM_CORE_EN_SHIFT 0
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#define CS35L45_CCM_CORE_EN_MASK BIT(0)
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/* REFCLK_INPUT */
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#define CS35L45_PLL_FORCE_EN_SHIFT 16
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#define CS35L45_PLL_FORCE_EN_MASK BIT(16)
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#define CS35L45_PLL_OPEN_LOOP_SHIFT 11
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#define CS35L45_PLL_OPEN_LOOP_MASK BIT(11)
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#define CS35L45_PLL_REFCLK_FREQ_SHIFT 5
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#define CS35L45_PLL_REFCLK_FREQ_MASK GENMASK(10, 5)
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#define CS35L45_PLL_REFCLK_EN_SHIFT 4
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#define CS35L45_PLL_REFCLK_EN_MASK BIT(4)
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#define CS35L45_PLL_REFCLK_SEL_SHIFT 0
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#define CS35L45_PLL_REFCLK_SEL_MASK GENMASK(2, 0)
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#define CS35L45_PLL_REFCLK_SEL_BCLK 0x0
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/* GLOBAL_SAMPLE_RATE */
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#define CS35L45_GLOBAL_FS_SHIFT 0
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#define CS35L45_GLOBAL_FS_MASK GENMASK(4, 0)
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#define CS35L45_48P0_KHZ 0x03
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#define CS35L45_96P0_KHZ 0x04
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#define CS35L45_44P100_KHZ 0x0B
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#define CS35L45_88P200_KHZ 0x0C
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/* ASP_ENABLES_1 */
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#define CS35L45_ASP_RX2_EN_SHIFT 17
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#define CS35L45_ASP_RX1_EN_SHIFT 16
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#define CS35L45_ASP_TX5_EN_SHIFT 4
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#define CS35L45_ASP_TX4_EN_SHIFT 3
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#define CS35L45_ASP_TX3_EN_SHIFT 2
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#define CS35L45_ASP_TX2_EN_SHIFT 1
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#define CS35L45_ASP_TX1_EN_SHIFT 0
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/* ASP_CONTROL2 */
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#define CS35L45_ASP_WIDTH_RX_SHIFT 24
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#define CS35L45_ASP_WIDTH_RX_MASK GENMASK(31, 24)
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#define CS35L45_ASP_WIDTH_TX_SHIFT 16
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#define CS35L45_ASP_WIDTH_TX_MASK GENMASK(23, 16)
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#define CS35L45_ASP_FMT_SHIFT 8
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#define CS35L45_ASP_FMT_MASK GENMASK(10, 8)
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#define CS35L45_ASP_BCLK_INV_SHIFT 6
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#define CS35L45_ASP_BCLK_INV_MASK BIT(6)
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#define CS35L45_ASP_FSYNC_INV_SHIFT 2
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#define CS35L45_ASP_FSYNC_INV_MASK BIT(2)
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#define CS35l45_ASP_FMT_DSP_A 0
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#define CS35L45_ASP_FMT_I2S 2
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/* ASP_CONTROL3 */
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#define CS35L45_ASP_DOUT_HIZ_CTRL_SHIFT 0
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#define CS35L45_ASP_DOUT_HIZ_CTRL_MASK GENMASK(1, 0)
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/* ASP_FRAME_CONTROL1 */
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#define CS35L45_ASP_TX4_SLOT_SHIFT 24
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#define CS35L45_ASP_TX4_SLOT_MASK GENMASK(29, 24)
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#define CS35L45_ASP_TX3_SLOT_SHIFT 16
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#define CS35L45_ASP_TX3_SLOT_MASK GENMASK(21, 16)
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#define CS35L45_ASP_TX2_SLOT_SHIFT 8
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#define CS35L45_ASP_TX2_SLOT_MASK GENMASK(13, 8)
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#define CS35L45_ASP_TX1_SLOT_SHIFT 0
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#define CS35L45_ASP_TX1_SLOT_MASK GENMASK(5, 0)
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#define CS35L45_ASP_TX_ALL_SLOTS (CS35L45_ASP_TX4_SLOT_MASK | \
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CS35L45_ASP_TX3_SLOT_MASK | \
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CS35L45_ASP_TX2_SLOT_MASK | \
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CS35L45_ASP_TX1_SLOT_MASK)
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/* ASP_FRAME_CONTROL5 */
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#define CS35L45_ASP_RX2_SLOT_SHIFT 8
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#define CS35L45_ASP_RX2_SLOT_MASK GENMASK(13, 8)
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#define CS35L45_ASP_RX1_SLOT_SHIFT 0
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#define CS35L45_ASP_RX1_SLOT_MASK GENMASK(5, 0)
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#define CS35L45_ASP_RX_ALL_SLOTS (CS35L45_ASP_RX2_SLOT_MASK | \
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CS35L45_ASP_RX1_SLOT_MASK)
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/* ASP_DATA_CONTROL1 */
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/* ASP_DATA_CONTROL5 */
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#define CS35L45_ASP_WL_SHIFT 0
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#define CS35L45_ASP_WL_MASK GENMASK(5, 0)
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/* HVLV_CONFIG */
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#define CS35L45_FORCE_LV_OPERATION 0x01
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#define CS35L45_FORCE_HV_OPERATION 0x02
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#define CS35L45_HVLV_OPERATION 0x03
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#define CS35L45_HVLV_MODE_SHIFT 0
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#define CS35L45_HVLV_MODE_MASK GENMASK(1, 0)
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/* AMP_PCM_CONTROL */
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#define CS35L45_AMP_VOL_PCM_SHIFT 0
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#define CS35L45_AMP_VOL_PCM_WIDTH 11
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/* AMP_PCM_HPF_TST */
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#define CS35l45_HPF_DEFAULT 0x00000000
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#define CS35L45_HPF_44P1 0x000108BD
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#define CS35L45_HPF_88P2 0x0001045F
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/* AMP_GAIN_PCM */
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#define CS35L45_AMP_GAIN_PCM_10DBV 0x00
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#define CS35L45_AMP_GAIN_PCM_13DBV 0x01
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#define CS35L45_AMP_GAIN_PCM_16DBV 0x02
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#define CS35L45_AMP_GAIN_PCM_19DBV 0x03
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#define CS35L45_AMP_GAIN_PCM_SHIFT 8
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#define CS35L45_AMP_GAIN_PCM_MASK GENMASK(9, 8)
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/* IRQ1_EINT_4 */
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#define CS35L45_OTP_BOOT_DONE_STS_MASK BIT(1)
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#define CS35L45_OTP_BUSY_MASK BIT(0)
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/* GPIOX_CTRL1 */
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#define CS35L45_GPIO_DIR_SHIFT 31
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#define CS35L45_GPIO_DIR_MASK BIT(31)
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#define CS35L45_GPIO_LVL_SHIFT 15
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#define CS35L45_GPIO_LVL_MASK BIT(15)
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#define CS35L45_GPIO_OP_CFG_SHIFT 14
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#define CS35L45_GPIO_OP_CFG_MASK BIT(14)
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#define CS35L45_GPIO_POL_SHIFT 12
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#define CS35L45_GPIO_POL_MASK BIT(12)
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/* SYNC_GPIO1, INTB_GPIO2_MCLK_REF, GPIO3 */
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#define CS35L45_GPIO_CTRL_SHIFT 20
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#define CS35L45_GPIO_CTRL_MASK GENMASK(22, 20)
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#define CS35L45_GPIO_INVERT_SHIFT 19
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#define CS35L45_GPIO_INVERT_MASK BIT(19)
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/* CS35L45_IRQ1_EINT_1 */
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#define CS35L45_BST_UVP_ERR_SHIFT 7
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#define CS35L45_BST_UVP_ERR_MASK BIT(7)
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#define CS35L45_BST_SHORT_ERR_SHIFT 8
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#define CS35L45_BST_SHORT_ERR_MASK BIT(8)
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#define CS35L45_TEMP_ERR_SHIFT 17
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#define CS35L45_TEMP_ERR_MASK BIT(17)
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#define CS35L45_MSM_GLOBAL_EN_ASSERT_SHIFT 22
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#define CS35L45_MSM_GLOBAL_EN_ASSERT_MASK BIT(22)
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#define CS35L45_UVLO_VDDBATT_ERR_SHIFT 29
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#define CS35L45_UVLO_VDDBATT_ERR_MASK BIT(29)
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#define CS35L45_AMP_SHORT_ERR_SHIFT 31
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#define CS35L45_AMP_SHORT_ERR_MASK BIT(31)
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/* CS35L45_IRQ1_EINT_2 */
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#define CS35L45_DSP_WDT_EXPIRE_SHIFT 4
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#define CS35L45_DSP_WDT_EXPIRE_MASK BIT(4)
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#define CS35L45_DSP_VIRT2_MBOX_SHIFT 21
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#define CS35L45_DSP_VIRT2_MBOX_MASK BIT(21)
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/* CS35L45_IRQ1_EINT_3 */
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#define CS35L45_PLL_LOCK_FLAG_SHIFT 1
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#define CS35L45_PLL_LOCK_FLAG_MASK BIT(1)
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#define CS35L45_PLL_UNLOCK_FLAG_RISE_SHIFT 4
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#define CS35L45_PLL_UNLOCK_FLAG_RISE_MASK BIT(4)
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#define CS35L45_AMP_CAL_ERR_SHIFT 25
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#define CS35L45_AMP_CAL_ERR_MASK BIT(25)
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/* CS35L45_IRQ1_EINT_18 */
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#define CS35L45_GLOBAL_ERROR_SHIFT 15
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#define CS35L45_GLOBAL_ERROR_MASK BIT(15)
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#define CS35L45_UVLO_VDDLV_ERR_SHIFT 16
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#define CS35L45_UVLO_VDDLV_ERR_MASK BIT(16)
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/* Mixer sources */
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#define CS35L45_PCM_SRC_MASK 0x7F
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#define CS35L45_PCM_SRC_ZERO 0x00
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#define CS35L45_PCM_SRC_ASP_RX1 0x08
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#define CS35L45_PCM_SRC_ASP_RX2 0x09
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#define CS35L45_PCM_SRC_VMON 0x18
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#define CS35L45_PCM_SRC_IMON 0x19
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#define CS35L45_PCM_SRC_ERR_VOL 0x20
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#define CS35L45_PCM_SRC_CLASSH_TGT 0x21
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#define CS35L45_PCM_SRC_VDD_BATTMON 0x28
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#define CS35L45_PCM_SRC_VDD_BSTMON 0x29
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#define CS35L45_PCM_SRC_DSP_TX1 0x32
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#define CS35L45_PCM_SRC_DSP_TX2 0x33
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#define CS35L45_PCM_SRC_TEMPMON 0x3A
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#define CS35L45_PCM_SRC_INTERPOLATOR 0x40
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#define CS35L45_PCM_SRC_IL_TARGET 0x48
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#define CS35L45_RESET_HOLD_US 2000
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#define CS35L45_RESET_US 2000
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#define CS35L45_POST_GLOBAL_EN_US 5000
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#define CS35L45_PRE_GLOBAL_DIS_US 3000
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/* WAKESRC_CTL */
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#define CS35L45_WKSRC_SYNC_GPIO1 BIT(0)
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#define CS35L45_WKSRC_INT_GPIO2 BIT(1)
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#define CS35L45_WKSRC_GPIO3 BIT(2)
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#define CS35L45_WKSRC_SPI BIT(3)
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#define CS35L45_WKSRC_I2C BIT(4)
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#define CS35L45_UPDT_WKCTL_SHIFT 15
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#define CS35L45_UPDT_WKCTL_MASK BIT(15)
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#define CS35L45_WKSRC_EN_SHIFT 8
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#define CS35L45_WKSRC_EN_MASK GENMASK(12, 8)
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#define CS35L45_WKSRC_POL_SHIFT 0
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#define CS35L45_WKSRC_POL_MASK GENMASK(3, 0)
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/* WAKEI2C_CTL */
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#define CS35L45_UPDT_WKI2C_SHIFT 15
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#define CS35L45_UPDT_WKI2C_MASK BIT(15)
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#define CS35L45_WKI2C_ADDR_SHIFT 0
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#define CS35L45_WKI2C_ADDR_MASK GENMASK(6, 0)
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#define CS35L45_SPI_MAX_FREQ 4000000
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enum cs35l45_cspl_mboxstate {
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CSPL_MBOX_STS_RUNNING = 0,
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CSPL_MBOX_STS_PAUSED = 1,
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CSPL_MBOX_STS_RDY_FOR_REINIT = 2,
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CSPL_MBOX_STS_HIBERNATE = 3,
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};
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enum cs35l45_cspl_mboxcmd {
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CSPL_MBOX_CMD_NONE = 0,
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CSPL_MBOX_CMD_PAUSE = 1,
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CSPL_MBOX_CMD_RESUME = 2,
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CSPL_MBOX_CMD_REINIT = 3,
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CSPL_MBOX_CMD_STOP_PRE_REINIT = 4,
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CSPL_MBOX_CMD_HIBERNATE = 5,
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CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6,
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CSPL_MBOX_CMD_UNKNOWN_CMD = -1,
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CSPL_MBOX_CMD_INVALID_SEQUENCE = -2,
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};
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enum control_bus_type {
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CONTROL_BUS_I2C = 0,
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CONTROL_BUS_SPI = 1,
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};
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enum amp_mode {
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AMP_MODE_SPK = 0,
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AMP_MODE_RCV = 1,
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};
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#define CS35L45_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S24_3LE| \
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SNDRV_PCM_FMTBIT_S24_LE)
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#define CS35L45_RATES (SNDRV_PCM_RATE_44100 | \
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SNDRV_PCM_RATE_48000 | \
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SNDRV_PCM_RATE_88200 | \
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SNDRV_PCM_RATE_96000)
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/*
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* IRQs
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*/
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#define CS35L45_IRQ(_irq, _name, _hand) \
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{ \
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.irq = CS35L45_ ## _irq ## _IRQ,\
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.name = _name, \
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.handler = _hand, \
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}
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struct cs35l45_irq {
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int irq;
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const char *name;
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irqreturn_t (*handler)(int irq, void *data);
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};
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#define CS35L45_REG_IRQ(_reg, _irq) \
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[CS35L45_ ## _irq ## _IRQ] = { \
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.reg_offset = (CS35L45_ ## _reg) - CS35L45_IRQ1_EINT_1, \
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.mask = CS35L45_ ## _irq ## _MASK \
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}
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enum cs35l45_irq_list {
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CS35L45_AMP_SHORT_ERR_IRQ,
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CS35L45_UVLO_VDDBATT_ERR_IRQ,
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CS35L45_BST_SHORT_ERR_IRQ,
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CS35L45_BST_UVP_ERR_IRQ,
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CS35L45_TEMP_ERR_IRQ,
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CS35L45_AMP_CAL_ERR_IRQ,
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CS35L45_UVLO_VDDLV_ERR_IRQ,
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CS35L45_GLOBAL_ERROR_IRQ,
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CS35L45_DSP_WDT_EXPIRE_IRQ,
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CS35L45_PLL_UNLOCK_FLAG_RISE_IRQ,
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CS35L45_PLL_LOCK_FLAG_IRQ,
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CS35L45_DSP_VIRT2_MBOX_IRQ,
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CS35L45_NUM_IRQ
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};
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#define CS35L45_MBOX3_CMD_MASK 0xFF
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#define CS35L45_MBOX3_CMD_SHIFT 0
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#define CS35L45_MBOX3_DATA_MASK 0xFFFFFF00
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#define CS35L45_MBOX3_DATA_SHIFT 8
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enum mbox3_events {
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EVENT_SPEAKER_STATUS = 0x66,
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EVENT_BOOT_DONE = 0x67,
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};
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struct cs35l45_private {
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struct wm_adsp dsp; /* needs to be first member */
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struct device *dev;
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struct regmap *regmap;
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struct gpio_desc *reset_gpio;
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struct regulator *vdd_batt;
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|
struct regulator *vdd_a;
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bool initialized;
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bool sysclk_set;
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u8 slot_width;
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|
u8 slot_count;
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int amplifier_mode;
|
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int irq_invert;
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|
int irq;
|
|
unsigned int i2c_addr;
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|
enum control_bus_type bus_type;
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|
struct regmap_irq_chip_data *irq_data;
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|
};
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|
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extern const struct dev_pm_ops cs35l45_pm_ops;
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extern const struct regmap_config cs35l45_i2c_regmap;
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extern const struct regmap_config cs35l45_spi_regmap;
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int cs35l45_apply_patch(struct cs35l45_private *cs35l45);
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int cs35l45_get_clk_freq_id(unsigned int freq);
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int cs35l45_probe(struct cs35l45_private *cs35l45);
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void cs35l45_remove(struct cs35l45_private *cs35l45);
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#endif /* CS35L45_H */
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