267 lines
		
	
	
		
			6.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			267 lines
		
	
	
		
			6.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0-or-later
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| /*
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|  * mpc8xxx_wdt.c - MPC8xx/MPC83xx/MPC86xx watchdog userspace interface
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|  *
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|  * Authors: Dave Updegraff <dave@cray.org>
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|  *	    Kumar Gala <galak@kernel.crashing.org>
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|  *		Attribution: from 83xx_wst: Florian Schirmer <jolt@tuxbox.org>
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|  *				..and from sc520_wdt
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|  * Copyright (c) 2008  MontaVista Software, Inc.
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|  *                     Anton Vorontsov <avorontsov@ru.mvista.com>
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|  *
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|  * Note: it appears that you can only actually ENABLE or DISABLE the thing
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|  * once after POR. Once enabled, you cannot disable, and vice versa.
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|  */
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| 
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| #include <linux/fs.h>
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| #include <linux/init.h>
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| #include <linux/kernel.h>
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| #include <linux/of_address.h>
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| #include <linux/of_platform.h>
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| #include <linux/module.h>
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| #include <linux/watchdog.h>
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| #include <linux/io.h>
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| #include <linux/uaccess.h>
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| #include <sysdev/fsl_soc.h>
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| 
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| #define WATCHDOG_TIMEOUT 10
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| 
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| struct mpc8xxx_wdt {
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| 	__be32 res0;
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| 	__be32 swcrr; /* System watchdog control register */
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| #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
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| #define SWCRR_SWF  0x00000008 /* Software Watchdog Freeze (mpc8xx). */
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| #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
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| #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/
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| #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
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| 	__be32 swcnr; /* System watchdog count register */
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| 	u8 res1[2];
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| 	__be16 swsrr; /* System watchdog service register */
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| 	u8 res2[0xF0];
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| };
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| 
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| struct mpc8xxx_wdt_type {
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| 	int prescaler;
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| 	bool hw_enabled;
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| 	u32 rsr_mask;
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| };
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| 
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| struct mpc8xxx_wdt_ddata {
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| 	struct mpc8xxx_wdt __iomem *base;
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| 	struct watchdog_device wdd;
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| 	spinlock_t lock;
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| 	u16 swtc;
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| };
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| 
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| static u16 timeout;
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| module_param(timeout, ushort, 0);
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| MODULE_PARM_DESC(timeout,
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| 	"Watchdog timeout in seconds. (1<timeout<65535, default="
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| 	__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
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| 
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| static bool reset = 1;
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| module_param(reset, bool, 0);
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| MODULE_PARM_DESC(reset,
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| 	"Watchdog Interrupt/Reset Mode. 0 = interrupt, 1 = reset");
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| 
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| static bool nowayout = WATCHDOG_NOWAYOUT;
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| module_param(nowayout, bool, 0);
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| MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
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| 		 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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| 
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| static void mpc8xxx_wdt_keepalive(struct mpc8xxx_wdt_ddata *ddata)
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| {
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| 	/* Ping the WDT */
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| 	spin_lock(&ddata->lock);
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| 	out_be16(&ddata->base->swsrr, 0x556c);
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| 	out_be16(&ddata->base->swsrr, 0xaa39);
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| 	spin_unlock(&ddata->lock);
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| }
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| 
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| static int mpc8xxx_wdt_start(struct watchdog_device *w)
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| {
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| 	struct mpc8xxx_wdt_ddata *ddata =
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| 		container_of(w, struct mpc8xxx_wdt_ddata, wdd);
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| 	u32 tmp = in_be32(&ddata->base->swcrr);
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| 
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| 	/* Good, fire up the show */
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| 	tmp &= ~(SWCRR_SWTC | SWCRR_SWF | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR);
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| 	tmp |= SWCRR_SWEN | SWCRR_SWPR | (ddata->swtc << 16);
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| 
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| 	if (reset)
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| 		tmp |= SWCRR_SWRI;
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| 
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| 	out_be32(&ddata->base->swcrr, tmp);
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| 
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| 	tmp = in_be32(&ddata->base->swcrr);
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| 	if (!(tmp & SWCRR_SWEN))
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| 		return -EOPNOTSUPP;
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| 
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| 	ddata->swtc = tmp >> 16;
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| 	set_bit(WDOG_HW_RUNNING, &ddata->wdd.status);
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| 
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| 	return 0;
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| }
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| 
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| static int mpc8xxx_wdt_ping(struct watchdog_device *w)
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| {
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| 	struct mpc8xxx_wdt_ddata *ddata =
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| 		container_of(w, struct mpc8xxx_wdt_ddata, wdd);
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| 
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| 	mpc8xxx_wdt_keepalive(ddata);
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| 	return 0;
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| }
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| 
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| static struct watchdog_info mpc8xxx_wdt_info = {
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| 	.options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT,
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| 	.firmware_version = 1,
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| 	.identity = "MPC8xxx",
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| };
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| 
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| static struct watchdog_ops mpc8xxx_wdt_ops = {
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| 	.owner = THIS_MODULE,
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| 	.start = mpc8xxx_wdt_start,
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| 	.ping = mpc8xxx_wdt_ping,
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| };
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| 
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| static int mpc8xxx_wdt_probe(struct platform_device *ofdev)
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| {
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| 	int ret;
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| 	struct resource *res;
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| 	const struct mpc8xxx_wdt_type *wdt_type;
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| 	struct mpc8xxx_wdt_ddata *ddata;
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| 	u32 freq = fsl_get_sys_freq();
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| 	bool enabled;
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| 	struct device *dev = &ofdev->dev;
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| 
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| 	wdt_type = of_device_get_match_data(dev);
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| 	if (!wdt_type)
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| 		return -EINVAL;
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| 
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| 	if (!freq || freq == -1)
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| 		return -EINVAL;
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| 
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| 	ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
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| 	if (!ddata)
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| 		return -ENOMEM;
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| 
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| 	ddata->base = devm_platform_ioremap_resource(ofdev, 0);
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| 	if (IS_ERR(ddata->base))
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| 		return PTR_ERR(ddata->base);
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| 
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| 	enabled = in_be32(&ddata->base->swcrr) & SWCRR_SWEN;
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| 	if (!enabled && wdt_type->hw_enabled) {
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| 		dev_info(dev, "could not be enabled in software\n");
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| 		return -ENODEV;
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| 	}
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| 
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| 	res = platform_get_resource(ofdev, IORESOURCE_MEM, 1);
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| 	if (res) {
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| 		bool status;
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| 		u32 __iomem *rsr = ioremap(res->start, resource_size(res));
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| 
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| 		if (!rsr)
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| 			return -ENOMEM;
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| 
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| 		status = in_be32(rsr) & wdt_type->rsr_mask;
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| 		ddata->wdd.bootstatus = status ? WDIOF_CARDRESET : 0;
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| 		 /* clear reset status bits related to watchdog timer */
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| 		out_be32(rsr, wdt_type->rsr_mask);
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| 		iounmap(rsr);
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| 
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| 		dev_info(dev, "Last boot was %scaused by watchdog\n",
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| 			 status ? "" : "not ");
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| 	}
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| 
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| 	spin_lock_init(&ddata->lock);
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| 
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| 	ddata->wdd.info = &mpc8xxx_wdt_info;
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| 	ddata->wdd.ops = &mpc8xxx_wdt_ops;
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| 
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| 	ddata->wdd.timeout = WATCHDOG_TIMEOUT;
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| 	watchdog_init_timeout(&ddata->wdd, timeout, dev);
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| 
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| 	watchdog_set_nowayout(&ddata->wdd, nowayout);
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| 
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| 	ddata->swtc = min(ddata->wdd.timeout * freq / wdt_type->prescaler,
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| 			  0xffffU);
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| 
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| 	/*
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| 	 * If the watchdog was previously enabled or we're running on
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| 	 * MPC8xxx, we should ping the wdt from the kernel until the
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| 	 * userspace handles it.
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| 	 */
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| 	if (enabled)
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| 		mpc8xxx_wdt_start(&ddata->wdd);
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| 
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| 	ddata->wdd.max_hw_heartbeat_ms = (ddata->swtc * wdt_type->prescaler) /
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| 					 (freq / 1000);
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| 	ddata->wdd.min_timeout = ddata->wdd.max_hw_heartbeat_ms / 1000;
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| 	if (ddata->wdd.timeout < ddata->wdd.min_timeout)
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| 		ddata->wdd.timeout = ddata->wdd.min_timeout;
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| 
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| 	ret = devm_watchdog_register_device(dev, &ddata->wdd);
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| 	if (ret)
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| 		return ret;
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| 
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| 	dev_info(dev,
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| 		 "WDT driver for MPC8xxx initialized. mode:%s timeout=%d sec\n",
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| 		 reset ? "reset" : "interrupt", ddata->wdd.timeout);
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| 
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| 	platform_set_drvdata(ofdev, ddata);
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| 	return 0;
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| }
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| 
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| static const struct of_device_id mpc8xxx_wdt_match[] = {
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| 	{
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| 		.compatible = "mpc83xx_wdt",
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| 		.data = &(struct mpc8xxx_wdt_type) {
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| 			.prescaler = 0x10000,
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| 			.rsr_mask = BIT(3), /* RSR Bit SWRS */
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| 		},
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| 	},
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| 	{
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| 		.compatible = "fsl,mpc8610-wdt",
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| 		.data = &(struct mpc8xxx_wdt_type) {
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| 			.prescaler = 0x10000,
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| 			.hw_enabled = true,
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| 			.rsr_mask = BIT(20), /* RSTRSCR Bit WDT_RR */
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| 		},
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| 	},
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| 	{
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| 		.compatible = "fsl,mpc823-wdt",
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| 		.data = &(struct mpc8xxx_wdt_type) {
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| 			.prescaler = 0x800,
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| 			.hw_enabled = true,
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| 			.rsr_mask = BIT(28), /* RSR Bit SWRS */
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| 		},
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| 	},
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| 	{},
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| };
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| MODULE_DEVICE_TABLE(of, mpc8xxx_wdt_match);
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| 
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| static struct platform_driver mpc8xxx_wdt_driver = {
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| 	.probe		= mpc8xxx_wdt_probe,
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| 	.driver = {
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| 		.name = "mpc8xxx_wdt",
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| 		.of_match_table = mpc8xxx_wdt_match,
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| 	},
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| };
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| 
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| static int __init mpc8xxx_wdt_init(void)
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| {
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| 	return platform_driver_register(&mpc8xxx_wdt_driver);
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| }
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| arch_initcall(mpc8xxx_wdt_init);
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| 
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| static void __exit mpc8xxx_wdt_exit(void)
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| {
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| 	platform_driver_unregister(&mpc8xxx_wdt_driver);
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| }
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| module_exit(mpc8xxx_wdt_exit);
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| 
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| MODULE_AUTHOR("Dave Updegraff, Kumar Gala");
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| MODULE_DESCRIPTION("Driver for watchdog timer in MPC8xx/MPC83xx/MPC86xx "
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| 		   "uProcessors");
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| MODULE_LICENSE("GPL");
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