319 lines
		
	
	
		
			8.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			319 lines
		
	
	
		
			8.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0-only
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| /*
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|  * NXP LPC18xx Watchdog Timer (WDT)
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|  *
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|  * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com>
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|  *
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|  * Notes
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|  * -----
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|  * The Watchdog consists of a fixed divide-by-4 clock pre-scaler and a 24-bit
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|  * counter which decrements on every clock cycle.
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|  */
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| 
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| #include <linux/clk.h>
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| #include <linux/io.h>
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| #include <linux/module.h>
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| #include <linux/of.h>
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| #include <linux/platform_device.h>
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| #include <linux/watchdog.h>
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| 
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| /* Registers */
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| #define LPC18XX_WDT_MOD			0x00
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| #define LPC18XX_WDT_MOD_WDEN		BIT(0)
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| #define LPC18XX_WDT_MOD_WDRESET		BIT(1)
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| 
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| #define LPC18XX_WDT_TC			0x04
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| #define LPC18XX_WDT_TC_MIN		0xff
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| #define LPC18XX_WDT_TC_MAX		0xffffff
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| 
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| #define LPC18XX_WDT_FEED		0x08
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| #define LPC18XX_WDT_FEED_MAGIC1		0xaa
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| #define LPC18XX_WDT_FEED_MAGIC2		0x55
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| 
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| #define LPC18XX_WDT_TV			0x0c
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| 
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| /* Clock pre-scaler */
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| #define LPC18XX_WDT_CLK_DIV		4
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| 
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| /* Timeout values in seconds */
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| #define LPC18XX_WDT_DEF_TIMEOUT		30U
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| 
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| static int heartbeat;
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| module_param(heartbeat, int, 0);
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| MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds (default="
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| 		 __MODULE_STRING(LPC18XX_WDT_DEF_TIMEOUT) ")");
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| 
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| static bool nowayout = WATCHDOG_NOWAYOUT;
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| module_param(nowayout, bool, 0);
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| MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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| 		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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| 
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| struct lpc18xx_wdt_dev {
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| 	struct watchdog_device	wdt_dev;
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| 	struct clk		*reg_clk;
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| 	struct clk		*wdt_clk;
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| 	unsigned long		clk_rate;
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| 	void __iomem		*base;
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| 	struct timer_list	timer;
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| 	spinlock_t		lock;
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| };
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| 
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| static int lpc18xx_wdt_feed(struct watchdog_device *wdt_dev)
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| {
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| 	struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
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| 	unsigned long flags;
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| 
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| 	/*
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| 	 * An abort condition will occur if an interrupt happens during the feed
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| 	 * sequence.
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| 	 */
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| 	spin_lock_irqsave(&lpc18xx_wdt->lock, flags);
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| 	writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
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| 	writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
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| 	spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags);
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| 
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| 	return 0;
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| }
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| 
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| static void lpc18xx_wdt_timer_feed(struct timer_list *t)
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| {
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| 	struct lpc18xx_wdt_dev *lpc18xx_wdt = from_timer(lpc18xx_wdt, t, timer);
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| 	struct watchdog_device *wdt_dev = &lpc18xx_wdt->wdt_dev;
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| 
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| 	lpc18xx_wdt_feed(wdt_dev);
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| 
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| 	/* Use safe value (1/2 of real timeout) */
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| 	mod_timer(&lpc18xx_wdt->timer, jiffies +
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| 		  msecs_to_jiffies((wdt_dev->timeout * MSEC_PER_SEC) / 2));
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| }
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| 
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| /*
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|  * Since LPC18xx Watchdog cannot be disabled in hardware, we must keep feeding
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|  * it with a timer until userspace watchdog software takes over.
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|  */
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| static int lpc18xx_wdt_stop(struct watchdog_device *wdt_dev)
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| {
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| 	struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
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| 
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| 	lpc18xx_wdt_timer_feed(&lpc18xx_wdt->timer);
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| 
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| 	return 0;
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| }
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| 
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| static void __lpc18xx_wdt_set_timeout(struct lpc18xx_wdt_dev *lpc18xx_wdt)
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| {
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| 	unsigned int val;
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| 
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| 	val = DIV_ROUND_UP(lpc18xx_wdt->wdt_dev.timeout * lpc18xx_wdt->clk_rate,
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| 			   LPC18XX_WDT_CLK_DIV);
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| 	writel(val, lpc18xx_wdt->base + LPC18XX_WDT_TC);
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| }
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| 
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| static int lpc18xx_wdt_set_timeout(struct watchdog_device *wdt_dev,
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| 				   unsigned int new_timeout)
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| {
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| 	struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
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| 
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| 	lpc18xx_wdt->wdt_dev.timeout = new_timeout;
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| 	__lpc18xx_wdt_set_timeout(lpc18xx_wdt);
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| 
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| 	return 0;
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| }
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| 
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| static unsigned int lpc18xx_wdt_get_timeleft(struct watchdog_device *wdt_dev)
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| {
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| 	struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
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| 	unsigned int val;
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| 
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| 	val = readl(lpc18xx_wdt->base + LPC18XX_WDT_TV);
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| 	return (val * LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate;
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| }
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| 
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| static int lpc18xx_wdt_start(struct watchdog_device *wdt_dev)
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| {
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| 	struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
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| 	unsigned int val;
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| 
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| 	if (timer_pending(&lpc18xx_wdt->timer))
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| 		del_timer(&lpc18xx_wdt->timer);
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| 
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| 	val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD);
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| 	val |= LPC18XX_WDT_MOD_WDEN;
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| 	val |= LPC18XX_WDT_MOD_WDRESET;
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| 	writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD);
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| 
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| 	/*
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| 	 * Setting the WDEN bit in the WDMOD register is not sufficient to
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| 	 * enable the Watchdog. A valid feed sequence must be completed after
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| 	 * setting WDEN before the Watchdog is capable of generating a reset.
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| 	 */
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| 	lpc18xx_wdt_feed(wdt_dev);
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| 
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| 	return 0;
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| }
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| 
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| static int lpc18xx_wdt_restart(struct watchdog_device *wdt_dev,
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| 			       unsigned long action, void *data)
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| {
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| 	struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
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| 	unsigned long flags;
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| 	int val;
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| 
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| 	/*
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| 	 * Incorrect feed sequence causes immediate watchdog reset if enabled.
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| 	 */
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| 	spin_lock_irqsave(&lpc18xx_wdt->lock, flags);
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| 
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| 	val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD);
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| 	val |= LPC18XX_WDT_MOD_WDEN;
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| 	val |= LPC18XX_WDT_MOD_WDRESET;
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| 	writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD);
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| 
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| 	writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
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| 	writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
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| 
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| 	writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
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| 	writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
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| 
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| 	spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags);
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| 
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| 	return 0;
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| }
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| 
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| static const struct watchdog_info lpc18xx_wdt_info = {
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| 	.identity	= "NXP LPC18xx Watchdog",
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| 	.options	= WDIOF_SETTIMEOUT |
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| 			  WDIOF_KEEPALIVEPING |
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| 			  WDIOF_MAGICCLOSE,
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| };
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| 
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| static const struct watchdog_ops lpc18xx_wdt_ops = {
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| 	.owner		= THIS_MODULE,
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| 	.start		= lpc18xx_wdt_start,
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| 	.stop		= lpc18xx_wdt_stop,
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| 	.ping		= lpc18xx_wdt_feed,
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| 	.set_timeout	= lpc18xx_wdt_set_timeout,
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| 	.get_timeleft	= lpc18xx_wdt_get_timeleft,
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| 	.restart        = lpc18xx_wdt_restart,
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| };
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| 
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| static void lpc18xx_clk_disable_unprepare(void *data)
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| {
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| 	clk_disable_unprepare(data);
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| }
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| 
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| static int lpc18xx_wdt_probe(struct platform_device *pdev)
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| {
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| 	struct lpc18xx_wdt_dev *lpc18xx_wdt;
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| 	struct device *dev = &pdev->dev;
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| 	int ret;
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| 
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| 	lpc18xx_wdt = devm_kzalloc(dev, sizeof(*lpc18xx_wdt), GFP_KERNEL);
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| 	if (!lpc18xx_wdt)
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| 		return -ENOMEM;
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| 
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| 	lpc18xx_wdt->base = devm_platform_ioremap_resource(pdev, 0);
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| 	if (IS_ERR(lpc18xx_wdt->base))
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| 		return PTR_ERR(lpc18xx_wdt->base);
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| 
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| 	lpc18xx_wdt->reg_clk = devm_clk_get(dev, "reg");
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| 	if (IS_ERR(lpc18xx_wdt->reg_clk)) {
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| 		dev_err(dev, "failed to get the reg clock\n");
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| 		return PTR_ERR(lpc18xx_wdt->reg_clk);
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| 	}
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| 
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| 	lpc18xx_wdt->wdt_clk = devm_clk_get(dev, "wdtclk");
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| 	if (IS_ERR(lpc18xx_wdt->wdt_clk)) {
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| 		dev_err(dev, "failed to get the wdt clock\n");
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| 		return PTR_ERR(lpc18xx_wdt->wdt_clk);
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| 	}
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| 
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| 	ret = clk_prepare_enable(lpc18xx_wdt->reg_clk);
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| 	if (ret) {
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| 		dev_err(dev, "could not prepare or enable sys clock\n");
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| 		return ret;
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| 	}
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| 	ret = devm_add_action_or_reset(dev, lpc18xx_clk_disable_unprepare,
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| 				       lpc18xx_wdt->reg_clk);
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| 	if (ret)
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| 		return ret;
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| 
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| 	ret = clk_prepare_enable(lpc18xx_wdt->wdt_clk);
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| 	if (ret) {
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| 		dev_err(dev, "could not prepare or enable wdt clock\n");
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| 		return ret;
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| 	}
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| 	ret = devm_add_action_or_reset(dev, lpc18xx_clk_disable_unprepare,
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| 				       lpc18xx_wdt->wdt_clk);
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| 	if (ret)
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| 		return ret;
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| 
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| 	/* We use the clock rate to calculate timeouts */
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| 	lpc18xx_wdt->clk_rate = clk_get_rate(lpc18xx_wdt->wdt_clk);
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| 	if (lpc18xx_wdt->clk_rate == 0) {
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| 		dev_err(dev, "failed to get clock rate\n");
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| 		return -EINVAL;
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| 	}
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| 
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| 	lpc18xx_wdt->wdt_dev.info = &lpc18xx_wdt_info;
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| 	lpc18xx_wdt->wdt_dev.ops = &lpc18xx_wdt_ops;
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| 
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| 	lpc18xx_wdt->wdt_dev.min_timeout = DIV_ROUND_UP(LPC18XX_WDT_TC_MIN *
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| 				LPC18XX_WDT_CLK_DIV, lpc18xx_wdt->clk_rate);
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| 
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| 	lpc18xx_wdt->wdt_dev.max_timeout = (LPC18XX_WDT_TC_MAX *
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| 				LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate;
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| 
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| 	lpc18xx_wdt->wdt_dev.timeout = min(lpc18xx_wdt->wdt_dev.max_timeout,
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| 					   LPC18XX_WDT_DEF_TIMEOUT);
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| 
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| 	spin_lock_init(&lpc18xx_wdt->lock);
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| 
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| 	lpc18xx_wdt->wdt_dev.parent = dev;
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| 	watchdog_set_drvdata(&lpc18xx_wdt->wdt_dev, lpc18xx_wdt);
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| 
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| 	watchdog_init_timeout(&lpc18xx_wdt->wdt_dev, heartbeat, dev);
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| 
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| 	__lpc18xx_wdt_set_timeout(lpc18xx_wdt);
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| 
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| 	timer_setup(&lpc18xx_wdt->timer, lpc18xx_wdt_timer_feed, 0);
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| 
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| 	watchdog_set_nowayout(&lpc18xx_wdt->wdt_dev, nowayout);
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| 	watchdog_set_restart_priority(&lpc18xx_wdt->wdt_dev, 128);
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| 
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| 	platform_set_drvdata(pdev, lpc18xx_wdt);
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| 
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| 	watchdog_stop_on_reboot(&lpc18xx_wdt->wdt_dev);
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| 	return devm_watchdog_register_device(dev, &lpc18xx_wdt->wdt_dev);
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| }
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| 
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| static int lpc18xx_wdt_remove(struct platform_device *pdev)
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| {
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| 	struct lpc18xx_wdt_dev *lpc18xx_wdt = platform_get_drvdata(pdev);
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| 
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| 	dev_warn(&pdev->dev, "I quit now, hardware will probably reboot!\n");
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| 	del_timer_sync(&lpc18xx_wdt->timer);
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| 
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| 	return 0;
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| }
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| 
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| static const struct of_device_id lpc18xx_wdt_match[] = {
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| 	{ .compatible = "nxp,lpc1850-wwdt" },
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| 	{}
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| };
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| MODULE_DEVICE_TABLE(of, lpc18xx_wdt_match);
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| 
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| static struct platform_driver lpc18xx_wdt_driver = {
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| 	.driver = {
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| 		.name = "lpc18xx-wdt",
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| 		.of_match_table	= lpc18xx_wdt_match,
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| 	},
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| 	.probe = lpc18xx_wdt_probe,
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| 	.remove = lpc18xx_wdt_remove,
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| };
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| module_platform_driver(lpc18xx_wdt_driver);
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| 
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| MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>");
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| MODULE_DESCRIPTION("NXP LPC18xx Watchdog Timer Driver");
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| MODULE_LICENSE("GPL v2");
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