177 lines
6.5 KiB
C
177 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
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/* true: device connected */
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#define PORT_CONNECT (1 << 0)
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/* true: port enabled */
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#define PORT_PE (1 << 1)
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/* bit 2 reserved and zeroed */
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/* true: port has an over-current condition */
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#define PORT_OC (1 << 3)
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/* true: port reset signaling asserted */
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#define PORT_RESET (1 << 4)
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/* Port Link State - bits 5:8
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* A read gives the current link PM state of the port,
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* a write with Link State Write Strobe set sets the link state.
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*/
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#define PORT_PLS_MASK (0xf << 5)
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#define XDEV_U0 (0x0 << 5)
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#define XDEV_U1 (0x1 << 5)
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#define XDEV_U2 (0x2 << 5)
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#define XDEV_U3 (0x3 << 5)
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#define XDEV_DISABLED (0x4 << 5)
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#define XDEV_RXDETECT (0x5 << 5)
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#define XDEV_INACTIVE (0x6 << 5)
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#define XDEV_POLLING (0x7 << 5)
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#define XDEV_RECOVERY (0x8 << 5)
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#define XDEV_HOT_RESET (0x9 << 5)
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#define XDEV_COMP_MODE (0xa << 5)
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#define XDEV_TEST_MODE (0xb << 5)
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#define XDEV_RESUME (0xf << 5)
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/* true: port has power (see HCC_PPC) */
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#define PORT_POWER (1 << 9)
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/* bits 10:13 indicate device speed:
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* 0 - undefined speed - port hasn't be initialized by a reset yet
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* 1 - full speed
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* 2 - low speed
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* 3 - high speed
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* 4 - super speed
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* 5-15 reserved
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*/
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#define DEV_SPEED_MASK (0xf << 10)
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#define XDEV_FS (0x1 << 10)
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#define XDEV_LS (0x2 << 10)
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#define XDEV_HS (0x3 << 10)
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#define XDEV_SS (0x4 << 10)
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#define XDEV_SSP (0x5 << 10)
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#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
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#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
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#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
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#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
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#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
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#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
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#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
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#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
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/* Bits 20:23 in the Slot Context are the speed for the device */
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#define SLOT_SPEED_FS (XDEV_FS << 10)
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#define SLOT_SPEED_LS (XDEV_LS << 10)
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#define SLOT_SPEED_HS (XDEV_HS << 10)
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#define SLOT_SPEED_SS (XDEV_SS << 10)
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#define SLOT_SPEED_SSP (XDEV_SSP << 10)
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/* Port Indicator Control */
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#define PORT_LED_OFF (0 << 14)
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#define PORT_LED_AMBER (1 << 14)
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#define PORT_LED_GREEN (2 << 14)
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#define PORT_LED_MASK (3 << 14)
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/* Port Link State Write Strobe - set this when changing link state */
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#define PORT_LINK_STROBE (1 << 16)
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/* true: connect status change */
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#define PORT_CSC (1 << 17)
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/* true: port enable change */
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#define PORT_PEC (1 << 18)
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/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
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* into an enabled state, and the device into the default state. A "warm" reset
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* also resets the link, forcing the device through the link training sequence.
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* SW can also look at the Port Reset register to see when warm reset is done.
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*/
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#define PORT_WRC (1 << 19)
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/* true: over-current change */
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#define PORT_OCC (1 << 20)
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/* true: reset change - 1 to 0 transition of PORT_RESET */
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#define PORT_RC (1 << 21)
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/* port link status change - set on some port link state transitions:
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* Transition Reason
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* ------------------------------------------------------------------------------
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* - U3 to Resume Wakeup signaling from a device
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* - Resume to Recovery to U0 USB 3.0 device resume
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* - Resume to U0 USB 2.0 device resume
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* - U3 to Recovery to U0 Software resume of USB 3.0 device complete
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* - U3 to U0 Software resume of USB 2.0 device complete
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* - U2 to U0 L1 resume of USB 2.1 device complete
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* - U0 to U0 (???) L1 entry rejection by USB 2.1 device
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* - U0 to disabled L1 entry error with USB 2.1 device
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* - Any state to inactive Error on USB 3.0 port
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*/
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#define PORT_PLC (1 << 22)
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/* port configure error change - port failed to configure its link partner */
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#define PORT_CEC (1 << 23)
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#define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
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PORT_RC | PORT_PLC | PORT_CEC)
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/* Cold Attach Status - xHC can set this bit to report device attached during
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* Sx state. Warm port reset should be perfomed to clear this bit and move port
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* to connected state.
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*/
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#define PORT_CAS (1 << 24)
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/* wake on connect (enable) */
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#define PORT_WKCONN_E (1 << 25)
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/* wake on disconnect (enable) */
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#define PORT_WKDISC_E (1 << 26)
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/* wake on over-current (enable) */
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#define PORT_WKOC_E (1 << 27)
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/* bits 28:29 reserved */
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/* true: device is non-removable - for USB 3.0 roothub emulation */
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#define PORT_DEV_REMOVE (1 << 30)
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/* Initiate a warm port reset - complete when PORT_WRC is '1' */
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#define PORT_WR (1 << 31)
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/* We mark duplicate entries with -1 */
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#define DUPLICATE_ENTRY ((u8)(-1))
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/* Port Power Management Status and Control - port_power_base bitmasks */
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/* Inactivity timer value for transitions into U1, in microseconds.
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* Timeout can be up to 127us. 0xFF means an infinite timeout.
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*/
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#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
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#define PORT_U1_TIMEOUT_MASK 0xff
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/* Inactivity timer value for transitions into U2 */
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#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
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#define PORT_U2_TIMEOUT_MASK (0xff << 8)
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/* Bits 24:31 for port testing */
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/* USB2 Protocol PORTSPMSC */
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#define PORT_L1S_MASK 7
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#define PORT_L1S_SUCCESS 1
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#define PORT_RWE (1 << 3)
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#define PORT_HIRD(p) (((p) & 0xf) << 4)
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#define PORT_HIRD_MASK (0xf << 4)
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#define PORT_L1DS_MASK (0xff << 8)
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#define PORT_L1DS(p) (((p) & 0xff) << 8)
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#define PORT_HLE (1 << 16)
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#define PORT_TEST_MODE_SHIFT 28
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/* USB3 Protocol PORTLI Port Link Information */
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#define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
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#define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
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/* USB2 Protocol PORTHLPMC */
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#define PORT_HIRDM(p)((p) & 3)
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#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
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#define PORT_BESLD(p)(((p) & 0xf) << 10)
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/* use 512 microseconds as USB2 LPM L1 default timeout. */
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#define XHCI_L1_TIMEOUT 512
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/* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
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* Safe to use with mixed HIRD and BESL systems (host and device) and is used
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* by other operating systems.
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*
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* XHCI 1.0 errata 8/14/12 Table 13 notes:
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* "Software should choose xHC BESL/BESLD field values that do not violate a
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* device's resume latency requirements,
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* e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
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* or not program values < '4' if BLC = '0' and a BESL device is attached.
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*/
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#define XHCI_DEFAULT_BESL 4
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/*
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* USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
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* to complete link training. usually link trainig completes much faster
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* so check status 10 times with 36ms sleep in places we need to wait for
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* polling to complete.
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*/
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#define XHCI_PORT_POLLING_LFPS_TIME 36
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