223 lines
		
	
	
		
			5.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			223 lines
		
	
	
		
			5.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* SPDX-License-Identifier: GPL-2.0 */
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| /*
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|  * xhci-dbc.h - xHCI debug capability early driver
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|  *
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|  * Copyright (C) 2016 Intel Corporation
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|  *
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|  * Author: Lu Baolu <baolu.lu@linux.intel.com>
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|  */
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| 
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| #ifndef __LINUX_XHCI_DBC_H
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| #define __LINUX_XHCI_DBC_H
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| 
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| #include <linux/types.h>
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| #include <linux/usb/ch9.h>
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| 
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| /*
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|  * xHCI Debug Capability Register interfaces:
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|  */
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| struct xdbc_regs {
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| 	__le32	capability;
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| 	__le32	doorbell;
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| 	__le32	ersts;		/* Event Ring Segment Table Size*/
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| 	__le32	__reserved_0;	/* 0c~0f reserved bits */
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| 	__le64	erstba;		/* Event Ring Segment Table Base Address */
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| 	__le64	erdp;		/* Event Ring Dequeue Pointer */
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| 	__le32	control;
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| 	__le32	status;
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| 	__le32	portsc;		/* Port status and control */
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| 	__le32	__reserved_1;	/* 2b~28 reserved bits */
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| 	__le64	dccp;		/* Debug Capability Context Pointer */
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| 	__le32	devinfo1;	/* Device Descriptor Info Register 1 */
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| 	__le32	devinfo2;	/* Device Descriptor Info Register 2 */
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| };
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| 
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| #define DEBUG_MAX_BURST(p)	(((p) >> 16) & 0xff)
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| 
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| #define CTRL_DBC_RUN		BIT(0)
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| #define CTRL_PORT_ENABLE	BIT(1)
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| #define CTRL_HALT_OUT_TR	BIT(2)
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| #define CTRL_HALT_IN_TR		BIT(3)
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| #define CTRL_DBC_RUN_CHANGE	BIT(4)
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| #define CTRL_DBC_ENABLE		BIT(31)
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| 
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| #define DCST_DEBUG_PORT(p)	(((p) >> 24) & 0xff)
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| 
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| #define PORTSC_CONN_STATUS	BIT(0)
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| #define PORTSC_CONN_CHANGE	BIT(17)
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| #define PORTSC_RESET_CHANGE	BIT(21)
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| #define PORTSC_LINK_CHANGE	BIT(22)
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| #define PORTSC_CONFIG_CHANGE	BIT(23)
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| 
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| /*
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|  * xHCI Debug Capability data structures:
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|  */
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| struct xdbc_trb {
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| 	__le32 field[4];
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| };
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| 
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| struct xdbc_erst_entry {
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| 	__le64	seg_addr;
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| 	__le32	seg_size;
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| 	__le32	__reserved_0;
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| };
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| 
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| struct xdbc_info_context {
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| 	__le64	string0;
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| 	__le64	manufacturer;
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| 	__le64	product;
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| 	__le64	serial;
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| 	__le32	length;
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| 	__le32	__reserved_0[7];
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| };
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| 
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| struct xdbc_ep_context {
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| 	__le32	ep_info1;
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| 	__le32	ep_info2;
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| 	__le64	deq;
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| 	__le32	tx_info;
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| 	__le32	__reserved_0[11];
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| };
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| 
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| struct xdbc_context {
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| 	struct xdbc_info_context	info;
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| 	struct xdbc_ep_context		out;
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| 	struct xdbc_ep_context		in;
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| };
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| 
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| #define XDBC_INFO_CONTEXT_SIZE		48
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| #define XDBC_MAX_STRING_LENGTH		64
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| #define XDBC_STRING_MANUFACTURER	"Linux Foundation"
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| #define XDBC_STRING_PRODUCT		"Linux USB GDB Target"
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| #define XDBC_STRING_SERIAL		"0001"
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| 
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| struct xdbc_strings {
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| 	char	string0[XDBC_MAX_STRING_LENGTH];
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| 	char	manufacturer[XDBC_MAX_STRING_LENGTH];
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| 	char	product[XDBC_MAX_STRING_LENGTH];
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| 	char	serial[XDBC_MAX_STRING_LENGTH];
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| };
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| 
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| #define XDBC_PROTOCOL		1	/* GNU Remote Debug Command Set */
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| #define XDBC_VENDOR_ID		0x1d6b	/* Linux Foundation 0x1d6b */
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| #define XDBC_PRODUCT_ID		0x0011	/* __le16 idProduct; device 0011 */
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| #define XDBC_DEVICE_REV		0x0010	/* 0.10 */
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| 
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| /*
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|  * xHCI Debug Capability software state structures:
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|  */
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| struct xdbc_segment {
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| 	struct xdbc_trb		*trbs;
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| 	dma_addr_t		dma;
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| };
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| 
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| #define XDBC_TRBS_PER_SEGMENT	256
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| 
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| struct xdbc_ring {
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| 	struct xdbc_segment	*segment;
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| 	struct xdbc_trb		*enqueue;
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| 	struct xdbc_trb		*dequeue;
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| 	u32			cycle_state;
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| };
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| 
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| /*
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|  * These are the "Endpoint ID" (also known as "Context Index") values for the
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|  * OUT Transfer Ring and the IN Transfer Ring of a Debug Capability Context data
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|  * structure.
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|  * According to the "eXtensible Host Controller Interface for Universal Serial
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|  * Bus (xHCI)" specification, section "7.6.3.2 Endpoint Contexts and Transfer
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|  * Rings", these should be 0 and 1, and those are the values AMD machines give
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|  * you; but Intel machines seem to use the formula from section "4.5.1 Device
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|  * Context Index", which is supposed to be used for the Device Context only.
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|  * Luckily the values from Intel don't overlap with those from AMD, so we can
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|  * just test for both.
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|  */
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| #define XDBC_EPID_OUT		0
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| #define XDBC_EPID_IN		1
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| #define XDBC_EPID_OUT_INTEL	2
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| #define XDBC_EPID_IN_INTEL	3
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| 
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| struct xdbc_state {
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| 	u16			vendor;
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| 	u16			device;
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| 	u32			bus;
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| 	u32			dev;
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| 	u32			func;
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| 	void __iomem		*xhci_base;
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| 	u64			xhci_start;
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| 	size_t			xhci_length;
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| 	int			port_number;
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| 
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| 	/* DbC register base */
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| 	struct xdbc_regs __iomem *xdbc_reg;
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| 
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| 	/* DbC table page */
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| 	dma_addr_t		table_dma;
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| 	void			*table_base;
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| 
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| 	/* event ring segment table */
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| 	dma_addr_t		erst_dma;
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| 	size_t			erst_size;
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| 	void			*erst_base;
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| 
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| 	/* event ring segments */
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| 	struct xdbc_ring	evt_ring;
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| 	struct xdbc_segment	evt_seg;
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| 
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| 	/* debug capability contexts */
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| 	dma_addr_t		dbcc_dma;
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| 	size_t			dbcc_size;
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| 	void			*dbcc_base;
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| 
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| 	/* descriptor strings */
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| 	dma_addr_t		string_dma;
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| 	size_t			string_size;
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| 	void			*string_base;
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| 
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| 	/* bulk OUT endpoint */
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| 	struct xdbc_ring	out_ring;
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| 	struct xdbc_segment	out_seg;
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| 	void			*out_buf;
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| 	dma_addr_t		out_dma;
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| 
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| 	/* bulk IN endpoint */
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| 	struct xdbc_ring	in_ring;
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| 	struct xdbc_segment	in_seg;
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| 	void			*in_buf;
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| 	dma_addr_t		in_dma;
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| 
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| 	u32			flags;
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| 
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| 	/* spinlock for early_xdbc_write() reentrancy */
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| 	raw_spinlock_t		lock;
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| };
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| 
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| #define XDBC_PCI_MAX_BUSES	256
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| #define XDBC_PCI_MAX_DEVICES	32
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| #define XDBC_PCI_MAX_FUNCTION	8
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| 
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| #define XDBC_TABLE_ENTRY_SIZE	64
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| #define XDBC_ERST_ENTRY_NUM	1
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| #define XDBC_DBCC_ENTRY_NUM	3
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| #define XDBC_STRING_ENTRY_NUM	4
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| 
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| /* Bits definitions for xdbc_state.flags: */
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| #define XDBC_FLAGS_INITIALIZED	BIT(0)
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| #define XDBC_FLAGS_IN_STALL	BIT(1)
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| #define XDBC_FLAGS_OUT_STALL	BIT(2)
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| #define XDBC_FLAGS_IN_PROCESS	BIT(3)
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| #define XDBC_FLAGS_OUT_PROCESS	BIT(4)
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| #define XDBC_FLAGS_CONFIGURED	BIT(5)
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| 
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| #define XDBC_MAX_PACKET		1024
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| 
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| /* Door bell target: */
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| #define OUT_EP_DOORBELL		0
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| #define IN_EP_DOORBELL		1
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| #define DOOR_BELL_TARGET(p)	(((p) & 0xff) << 8)
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| 
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| #define xdbc_read64(regs)	xhci_read_64(NULL, (regs))
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| #define xdbc_write64(val, regs)	xhci_write_64(NULL, (val), (regs))
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| 
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| #endif /* __LINUX_XHCI_DBC_H */
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