99 lines
3.5 KiB
C
99 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Thunderbolt driver - NHI driver
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*
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* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
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* Copyright (C) 2018, Intel Corporation
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*/
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#ifndef DSL3510_H_
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#define DSL3510_H_
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#include <linux/thunderbolt.h>
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enum nhi_fw_mode {
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NHI_FW_SAFE_MODE,
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NHI_FW_AUTH_MODE,
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NHI_FW_EP_MODE,
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NHI_FW_CM_MODE,
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};
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enum nhi_mailbox_cmd {
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NHI_MAILBOX_SAVE_DEVS = 0x05,
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NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06,
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NHI_MAILBOX_DRV_UNLOADS = 0x07,
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NHI_MAILBOX_DISCONNECT_PA = 0x10,
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NHI_MAILBOX_DISCONNECT_PB = 0x11,
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NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23,
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};
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int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data);
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enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi);
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/**
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* struct tb_nhi_ops - NHI specific optional operations
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* @init: NHI specific initialization
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* @suspend_noirq: NHI specific suspend_noirq hook
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* @resume_noirq: NHI specific resume_noirq hook
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* @runtime_suspend: NHI specific runtime_suspend hook
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* @runtime_resume: NHI specific runtime_resume hook
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* @shutdown: NHI specific shutdown
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*/
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struct tb_nhi_ops {
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int (*init)(struct tb_nhi *nhi);
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int (*suspend_noirq)(struct tb_nhi *nhi, bool wakeup);
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int (*resume_noirq)(struct tb_nhi *nhi);
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int (*runtime_suspend)(struct tb_nhi *nhi);
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int (*runtime_resume)(struct tb_nhi *nhi);
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void (*shutdown)(struct tb_nhi *nhi);
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};
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extern const struct tb_nhi_ops icl_nhi_ops;
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/*
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* PCI IDs used in this driver from Win Ridge forward. There is no
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* need for the PCI quirk anymore as we will use ICM also on Apple
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* hardware.
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*/
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#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_2C_NHI 0x1134
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#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_4C_NHI 0x1137
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#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI 0x157d
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#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI 0x15bf
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c0
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI 0x15d2
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE 0x15d3
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI 0x15d9
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE 0x15da
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI 0x15dd
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE 0x15e7
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI 0x15e8
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE 0x15ea
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI 0x15eb
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE 0x15ef
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#define PCI_DEVICE_ID_INTEL_ADL_NHI0 0x463e
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#define PCI_DEVICE_ID_INTEL_ADL_NHI1 0x466d
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#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI 0x5781
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#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI 0x5784
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#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_80G_BRIDGE 0x5786
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#define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_40G_BRIDGE 0x57a4
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#define PCI_DEVICE_ID_INTEL_MTL_M_NHI0 0x7eb2
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#define PCI_DEVICE_ID_INTEL_MTL_P_NHI0 0x7ec2
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#define PCI_DEVICE_ID_INTEL_MTL_P_NHI1 0x7ec3
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#define PCI_DEVICE_ID_INTEL_ICL_NHI1 0x8a0d
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#define PCI_DEVICE_ID_INTEL_ICL_NHI0 0x8a17
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#define PCI_DEVICE_ID_INTEL_TGL_NHI0 0x9a1b
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#define PCI_DEVICE_ID_INTEL_TGL_NHI1 0x9a1d
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#define PCI_DEVICE_ID_INTEL_TGL_H_NHI0 0x9a1f
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#define PCI_DEVICE_ID_INTEL_TGL_H_NHI1 0x9a21
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#define PCI_DEVICE_ID_INTEL_RPL_NHI0 0xa73e
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#define PCI_DEVICE_ID_INTEL_RPL_NHI1 0xa76d
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#define PCI_DEVICE_ID_INTEL_LNL_NHI0 0xa833
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#define PCI_DEVICE_ID_INTEL_LNL_NHI1 0xa834
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#define PCI_CLASS_SERIAL_USB_USB4 0x0c0340
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#endif
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