343 lines
11 KiB
C
343 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* wd33c93.h - Linux device driver definitions for the
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* Commodore Amiga A2091/590 SCSI controller card
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*
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* IMPORTANT: This file is for version 1.25 - 09/Jul/1997
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*
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* Copyright (c) 1996 John Shifflett, GeoLog Consulting
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* john@geolog.com
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* jshiffle@netcom.com
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*/
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#ifndef WD33C93_H
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#define WD33C93_H
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#define PROC_INTERFACE /* add code for /proc/scsi/wd33c93/xxx interface */
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#ifdef PROC_INTERFACE
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#define PROC_STATISTICS /* add code for keeping various real time stats */
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#endif
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#define SYNC_DEBUG /* extra info on sync negotiation printed */
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#define DEBUGGING_ON /* enable command-line debugging bitmask */
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#define DEBUG_DEFAULTS 0 /* default debugging bitmask */
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#ifdef DEBUGGING_ON
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#define DB(f,a) if (hostdata->args & (f)) a;
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#else
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#define DB(f,a)
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#endif
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#define uchar unsigned char
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/* wd register names */
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#define WD_OWN_ID 0x00
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#define WD_CONTROL 0x01
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#define WD_TIMEOUT_PERIOD 0x02
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#define WD_CDB_1 0x03
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#define WD_CDB_2 0x04
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#define WD_CDB_3 0x05
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#define WD_CDB_4 0x06
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#define WD_CDB_5 0x07
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#define WD_CDB_6 0x08
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#define WD_CDB_7 0x09
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#define WD_CDB_8 0x0a
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#define WD_CDB_9 0x0b
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#define WD_CDB_10 0x0c
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#define WD_CDB_11 0x0d
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#define WD_CDB_12 0x0e
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#define WD_TARGET_LUN 0x0f
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#define WD_COMMAND_PHASE 0x10
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#define WD_SYNCHRONOUS_TRANSFER 0x11
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#define WD_TRANSFER_COUNT_MSB 0x12
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#define WD_TRANSFER_COUNT 0x13
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#define WD_TRANSFER_COUNT_LSB 0x14
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#define WD_DESTINATION_ID 0x15
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#define WD_SOURCE_ID 0x16
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#define WD_SCSI_STATUS 0x17
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#define WD_COMMAND 0x18
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#define WD_DATA 0x19
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#define WD_QUEUE_TAG 0x1a
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#define WD_AUXILIARY_STATUS 0x1f
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/* WD commands */
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#define WD_CMD_RESET 0x00
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#define WD_CMD_ABORT 0x01
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#define WD_CMD_ASSERT_ATN 0x02
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#define WD_CMD_NEGATE_ACK 0x03
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#define WD_CMD_DISCONNECT 0x04
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#define WD_CMD_RESELECT 0x05
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#define WD_CMD_SEL_ATN 0x06
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#define WD_CMD_SEL 0x07
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#define WD_CMD_SEL_ATN_XFER 0x08
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#define WD_CMD_SEL_XFER 0x09
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#define WD_CMD_RESEL_RECEIVE 0x0a
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#define WD_CMD_RESEL_SEND 0x0b
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#define WD_CMD_WAIT_SEL_RECEIVE 0x0c
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#define WD_CMD_TRANS_ADDR 0x18
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#define WD_CMD_TRANS_INFO 0x20
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#define WD_CMD_TRANSFER_PAD 0x21
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#define WD_CMD_SBT_MODE 0x80
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/* ASR register */
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#define ASR_INT (0x80)
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#define ASR_LCI (0x40)
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#define ASR_BSY (0x20)
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#define ASR_CIP (0x10)
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#define ASR_PE (0x02)
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#define ASR_DBR (0x01)
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/* SCSI Bus Phases */
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#define PHS_DATA_OUT 0x00
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#define PHS_DATA_IN 0x01
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#define PHS_COMMAND 0x02
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#define PHS_STATUS 0x03
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#define PHS_MESS_OUT 0x06
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#define PHS_MESS_IN 0x07
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/* Command Status Register definitions */
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/* reset state interrupts */
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#define CSR_RESET 0x00
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#define CSR_RESET_AF 0x01
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/* successful completion interrupts */
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#define CSR_RESELECT 0x10
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#define CSR_SELECT 0x11
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#define CSR_SEL_XFER_DONE 0x16
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#define CSR_XFER_DONE 0x18
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/* paused or aborted interrupts */
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#define CSR_MSGIN 0x20
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#define CSR_SDP 0x21
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#define CSR_SEL_ABORT 0x22
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#define CSR_RESEL_ABORT 0x25
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#define CSR_RESEL_ABORT_AM 0x27
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#define CSR_ABORT 0x28
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/* terminated interrupts */
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#define CSR_INVALID 0x40
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#define CSR_UNEXP_DISC 0x41
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#define CSR_TIMEOUT 0x42
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#define CSR_PARITY 0x43
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#define CSR_PARITY_ATN 0x44
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#define CSR_BAD_STATUS 0x45
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#define CSR_UNEXP 0x48
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/* service required interrupts */
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#define CSR_RESEL 0x80
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#define CSR_RESEL_AM 0x81
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#define CSR_DISC 0x85
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#define CSR_SRV_REQ 0x88
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/* Own ID/CDB Size register */
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#define OWNID_EAF 0x08
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#define OWNID_EHP 0x10
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#define OWNID_RAF 0x20
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#define OWNID_FS_8 0x00
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#define OWNID_FS_12 0x40
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#define OWNID_FS_16 0x80
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/* define these so we don't have to change a2091.c, etc. */
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#define WD33C93_FS_8_10 OWNID_FS_8
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#define WD33C93_FS_12_15 OWNID_FS_12
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#define WD33C93_FS_16_20 OWNID_FS_16
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/* pass input-clock explicitly. accepted mhz values are 8-10,12-20 */
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#define WD33C93_FS_MHZ(mhz) (mhz)
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/* Control register */
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#define CTRL_HSP 0x01
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#define CTRL_HA 0x02
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#define CTRL_IDI 0x04
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#define CTRL_EDI 0x08
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#define CTRL_HHP 0x10
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#define CTRL_POLLED 0x00
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#define CTRL_BURST 0x20
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#define CTRL_BUS 0x40
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#define CTRL_DMA 0x80
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/* Timeout Period register */
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#define TIMEOUT_PERIOD_VALUE 20 /* 20 = 200 ms */
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/* Synchronous Transfer Register */
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#define STR_FSS 0x80
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/* Destination ID register */
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#define DSTID_DPD 0x40
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#define DATA_OUT_DIR 0
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#define DATA_IN_DIR 1
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#define DSTID_SCC 0x80
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/* Source ID register */
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#define SRCID_MASK 0x07
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#define SRCID_SIV 0x08
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#define SRCID_DSP 0x20
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#define SRCID_ES 0x40
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#define SRCID_ER 0x80
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/* This is what the 3393 chip looks like to us */
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typedef struct {
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#ifdef CONFIG_WD33C93_PIO
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unsigned int SASR;
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unsigned int SCMD;
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#else
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volatile unsigned char *SASR;
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volatile unsigned char *SCMD;
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#endif
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} wd33c93_regs;
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typedef int (*dma_setup_t) (struct scsi_cmnd *SCpnt, int dir_in);
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typedef void (*dma_stop_t) (struct Scsi_Host *instance,
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struct scsi_cmnd *SCpnt, int status);
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#define ILLEGAL_STATUS_BYTE 0xff
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#define DEFAULT_SX_PER 376 /* (ns) fairly safe */
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#define DEFAULT_SX_OFF 0 /* aka async */
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#define OPTIMUM_SX_PER 252 /* (ns) best we can do (mult-of-4) */
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#define OPTIMUM_SX_OFF 12 /* size of wd3393 fifo */
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struct sx_period {
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unsigned int period_ns;
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uchar reg_value;
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};
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/* FEF: defines for hostdata->dma_buffer_pool */
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#define BUF_CHIP_ALLOCED 0
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#define BUF_SCSI_ALLOCED 1
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struct WD33C93_hostdata {
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struct Scsi_Host *next;
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wd33c93_regs regs;
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spinlock_t lock;
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uchar clock_freq;
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uchar chip; /* what kind of wd33c93? */
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uchar microcode; /* microcode rev */
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uchar dma_buffer_pool; /* FEF: buffer from chip_ram? */
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int dma_dir; /* data transfer dir. */
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dma_setup_t dma_setup;
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dma_stop_t dma_stop;
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unsigned int dma_xfer_mask;
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uchar *dma_bounce_buffer;
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unsigned int dma_bounce_len;
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volatile uchar busy[8]; /* index = target, bit = lun */
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volatile struct scsi_cmnd *input_Q; /* commands waiting to be started */
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volatile struct scsi_cmnd *selecting; /* trying to select this command */
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volatile struct scsi_cmnd *connected; /* currently connected command */
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volatile struct scsi_cmnd *disconnected_Q;/* commands waiting for reconnect */
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uchar state; /* what we are currently doing */
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uchar dma; /* current state of DMA (on/off) */
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uchar level2; /* extent to which Level-2 commands are used */
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uchar disconnect; /* disconnect/reselect policy */
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unsigned int args; /* set from command-line argument */
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uchar incoming_msg[8]; /* filled during message_in phase */
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int incoming_ptr; /* mainly used with EXTENDED messages */
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uchar outgoing_msg[8]; /* send this during next message_out */
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int outgoing_len; /* length of outgoing message */
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unsigned int default_sx_per; /* default transfer period for SCSI bus */
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uchar sync_xfer[8]; /* sync_xfer reg settings per target */
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uchar sync_stat[8]; /* status of sync negotiation per target */
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uchar no_sync; /* bitmask: don't do sync on these targets */
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uchar no_dma; /* set this flag to disable DMA */
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uchar dma_mode; /* DMA Burst Mode or Single Byte DMA */
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uchar fast; /* set this flag to enable Fast SCSI */
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struct sx_period sx_table[9]; /* transfer periods for actual DTC-setting */
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#ifdef PROC_INTERFACE
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uchar proc; /* bitmask: what's in proc output */
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#ifdef PROC_STATISTICS
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unsigned long cmd_cnt[8]; /* # of commands issued per target */
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unsigned long int_cnt; /* # of interrupts serviced */
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unsigned long pio_cnt; /* # of pio data transfers */
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unsigned long dma_cnt; /* # of DMA data transfers */
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unsigned long disc_allowed_cnt[8]; /* # of disconnects allowed per target */
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unsigned long disc_done_cnt[8]; /* # of disconnects done per target*/
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#endif
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#endif
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};
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/* defines for hostdata->chip */
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#define C_WD33C93 0
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#define C_WD33C93A 1
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#define C_WD33C93B 2
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#define C_UNKNOWN_CHIP 100
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/* defines for hostdata->state */
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#define S_UNCONNECTED 0
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#define S_SELECTING 1
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#define S_RUNNING_LEVEL2 2
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#define S_CONNECTED 3
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#define S_PRE_TMP_DISC 4
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#define S_PRE_CMP_DISC 5
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/* defines for hostdata->dma */
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#define D_DMA_OFF 0
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#define D_DMA_RUNNING 1
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/* defines for hostdata->level2 */
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/* NOTE: only the first 3 are implemented so far */
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#define L2_NONE 1 /* no combination commands - we get lots of ints */
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#define L2_SELECT 2 /* start with SEL_ATN_XFER, but never resume it */
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#define L2_BASIC 3 /* resume after STATUS ints & RDP messages */
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#define L2_DATA 4 /* resume after DATA_IN/OUT ints */
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#define L2_MOST 5 /* resume after anything except a RESELECT int */
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#define L2_RESELECT 6 /* resume after everything, including RESELECT ints */
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#define L2_ALL 7 /* always resume */
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/* defines for hostdata->disconnect */
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#define DIS_NEVER 0
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#define DIS_ADAPTIVE 1
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#define DIS_ALWAYS 2
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/* defines for hostdata->args */
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#define DB_TEST1 1<<0
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#define DB_TEST2 1<<1
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#define DB_QUEUE_COMMAND 1<<2
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#define DB_EXECUTE 1<<3
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#define DB_INTR 1<<4
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#define DB_TRANSFER 1<<5
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#define DB_MASK 0x3f
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/* defines for hostdata->sync_stat[] */
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#define SS_UNSET 0
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#define SS_FIRST 1
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#define SS_WAITING 2
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#define SS_SET 3
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/* defines for hostdata->proc */
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#define PR_VERSION 1<<0
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#define PR_INFO 1<<1
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#define PR_STATISTICS 1<<2
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#define PR_CONNECTED 1<<3
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#define PR_INPUTQ 1<<4
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#define PR_DISCQ 1<<5
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#define PR_TEST 1<<6
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#define PR_STOP 1<<7
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void wd33c93_init (struct Scsi_Host *instance, const wd33c93_regs regs,
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dma_setup_t setup, dma_stop_t stop, int clock_freq);
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int wd33c93_abort (struct scsi_cmnd *cmd);
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int wd33c93_queuecommand (struct Scsi_Host *h, struct scsi_cmnd *cmd);
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void wd33c93_intr (struct Scsi_Host *instance);
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int wd33c93_show_info(struct seq_file *, struct Scsi_Host *);
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int wd33c93_write_info(struct Scsi_Host *, char *, int);
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int wd33c93_host_reset (struct scsi_cmnd *);
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#endif /* WD33C93_H */
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