185 lines
		
	
	
		
			5.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			185 lines
		
	
	
		
			5.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0-or-later
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| /*
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|  * The Netronix embedded controller is a microcontroller found in some
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|  * e-book readers designed by the original design manufacturer Netronix, Inc.
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|  * It contains RTC, battery monitoring, system power management, and PWM
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|  * functionality.
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|  *
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|  * This driver implements PWM output.
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|  *
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|  * Copyright 2020 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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|  *
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|  * Limitations:
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|  * - The get_state callback is not implemented, because the current state of
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|  *   the PWM output can't be read back from the hardware.
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|  * - The hardware can only generate normal polarity output.
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|  * - The period and duty cycle can't be changed together in one atomic action.
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|  */
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| 
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| #include <linux/mfd/ntxec.h>
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| #include <linux/module.h>
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| #include <linux/platform_device.h>
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| #include <linux/pwm.h>
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| #include <linux/regmap.h>
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| #include <linux/types.h>
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| 
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| struct ntxec_pwm {
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| 	struct device *dev;
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| 	struct ntxec *ec;
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| 	struct pwm_chip chip;
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| };
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| 
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| static struct ntxec_pwm *ntxec_pwm_from_chip(struct pwm_chip *chip)
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| {
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| 	return container_of(chip, struct ntxec_pwm, chip);
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| }
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| 
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| #define NTXEC_REG_AUTO_OFF_HI	0xa1
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| #define NTXEC_REG_AUTO_OFF_LO	0xa2
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| #define NTXEC_REG_ENABLE	0xa3
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| #define NTXEC_REG_PERIOD_LOW	0xa4
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| #define NTXEC_REG_PERIOD_HIGH	0xa5
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| #define NTXEC_REG_DUTY_LOW	0xa6
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| #define NTXEC_REG_DUTY_HIGH	0xa7
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| 
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| /*
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|  * The time base used in the EC is 8MHz, or 125ns. Period and duty cycle are
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|  * measured in this unit.
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|  */
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| #define TIME_BASE_NS 125
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| 
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| /*
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|  * The maximum input value (in nanoseconds) is determined by the time base and
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|  * the range of the hardware registers that hold the converted value.
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|  * It fits into 32 bits, so we can do our calculations in 32 bits as well.
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|  */
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| #define MAX_PERIOD_NS (TIME_BASE_NS * 0xffff)
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| 
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| static int ntxec_pwm_set_raw_period_and_duty_cycle(struct pwm_chip *chip,
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| 						   int period, int duty)
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| {
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| 	struct ntxec_pwm *priv = ntxec_pwm_from_chip(chip);
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| 
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| 	/*
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| 	 * Changes to the period and duty cycle take effect as soon as the
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| 	 * corresponding low byte is written, so the hardware may be configured
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| 	 * to an inconsistent state after the period is written and before the
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| 	 * duty cycle is fully written. If, in such a case, the old duty cycle
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| 	 * is longer than the new period, the EC may output 100% for a moment.
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| 	 *
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| 	 * To minimize the time between the changes to period and duty cycle
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| 	 * taking effect, the writes are interleaved.
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| 	 */
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| 
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| 	struct reg_sequence regs[] = {
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| 		{ NTXEC_REG_PERIOD_HIGH, ntxec_reg8(period >> 8) },
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| 		{ NTXEC_REG_DUTY_HIGH, ntxec_reg8(duty >> 8) },
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| 		{ NTXEC_REG_PERIOD_LOW, ntxec_reg8(period) },
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| 		{ NTXEC_REG_DUTY_LOW, ntxec_reg8(duty) },
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| 	};
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| 
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| 	return regmap_multi_reg_write(priv->ec->regmap, regs, ARRAY_SIZE(regs));
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| }
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| 
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| static int ntxec_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm_dev,
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| 			   const struct pwm_state *state)
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| {
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| 	struct ntxec_pwm *priv = ntxec_pwm_from_chip(chip);
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| 	unsigned int period, duty;
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| 	int res;
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| 
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| 	if (state->polarity != PWM_POLARITY_NORMAL)
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| 		return -EINVAL;
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| 
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| 	period = min_t(u64, state->period, MAX_PERIOD_NS);
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| 	duty   = min_t(u64, state->duty_cycle, period);
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| 
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| 	period /= TIME_BASE_NS;
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| 	duty   /= TIME_BASE_NS;
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| 
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| 	/*
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| 	 * Writing a duty cycle of zero puts the device into a state where
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| 	 * writing a higher duty cycle doesn't result in the brightness that it
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| 	 * usually results in. This can be fixed by cycling the ENABLE register.
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| 	 *
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| 	 * As a workaround, write ENABLE=0 when the duty cycle is zero.
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| 	 * The case that something has previously set the duty cycle to zero
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| 	 * but ENABLE=1, is not handled.
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| 	 */
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| 	if (state->enabled && duty != 0) {
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| 		res = ntxec_pwm_set_raw_period_and_duty_cycle(chip, period, duty);
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| 		if (res)
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| 			return res;
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| 
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| 		res = regmap_write(priv->ec->regmap, NTXEC_REG_ENABLE, ntxec_reg8(1));
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| 		if (res)
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| 			return res;
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| 
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| 		/* Disable the auto-off timer */
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| 		res = regmap_write(priv->ec->regmap, NTXEC_REG_AUTO_OFF_HI, ntxec_reg8(0xff));
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| 		if (res)
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| 			return res;
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| 
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| 		return regmap_write(priv->ec->regmap, NTXEC_REG_AUTO_OFF_LO, ntxec_reg8(0xff));
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| 	} else {
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| 		return regmap_write(priv->ec->regmap, NTXEC_REG_ENABLE, ntxec_reg8(0));
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| 	}
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| }
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| 
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| static const struct pwm_ops ntxec_pwm_ops = {
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| 	.owner = THIS_MODULE,
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| 	.apply = ntxec_pwm_apply,
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| 	/*
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| 	 * No .get_state callback, because the current state cannot be read
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| 	 * back from the hardware.
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| 	 */
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| };
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| 
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| static int ntxec_pwm_probe(struct platform_device *pdev)
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| {
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| 	struct ntxec *ec = dev_get_drvdata(pdev->dev.parent);
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| 	struct ntxec_pwm *priv;
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| 	struct pwm_chip *chip;
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| 
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| 	pdev->dev.of_node = pdev->dev.parent->of_node;
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| 
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| 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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| 	if (!priv)
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| 		return -ENOMEM;
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| 
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| 	priv->ec = ec;
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| 	priv->dev = &pdev->dev;
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| 
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| 	platform_set_drvdata(pdev, priv);
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| 
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| 	chip = &priv->chip;
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| 	chip->dev = &pdev->dev;
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| 	chip->ops = &ntxec_pwm_ops;
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| 	chip->base = -1;
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| 	chip->npwm = 1;
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| 
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| 	return pwmchip_add(chip);
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| }
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| 
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| static int ntxec_pwm_remove(struct platform_device *pdev)
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| {
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| 	struct ntxec_pwm *priv = platform_get_drvdata(pdev);
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| 	struct pwm_chip *chip = &priv->chip;
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| 
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| 	return pwmchip_remove(chip);
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| }
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| 
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| static struct platform_driver ntxec_pwm_driver = {
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| 	.driver = {
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| 		.name = "ntxec-pwm",
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| 	},
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| 	.probe = ntxec_pwm_probe,
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| 	.remove = ntxec_pwm_remove,
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| };
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| module_platform_driver(ntxec_pwm_driver);
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| 
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| MODULE_AUTHOR("Jonathan Neuschäfer <j.neuschaefer@gmx.net>");
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| MODULE_DESCRIPTION("PWM driver for Netronix EC");
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| MODULE_LICENSE("GPL");
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| MODULE_ALIAS("platform:ntxec-pwm");
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