1362 lines
24 KiB
C
1362 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved.
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*/
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#include <soc/tegra/mc.h>
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#include <dt-bindings/memory/tegra194-mc.h>
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#include "mc.h"
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static const struct tegra_mc_client tegra194_mc_clients[] = {
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{
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.id = TEGRA194_MEMORY_CLIENT_PTCR,
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.name = "ptcr",
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.sid = TEGRA194_SID_PASSTHROUGH,
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.regs = {
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.sid = {
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.override = 0x000,
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.security = 0x004,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_MIU7R,
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.name = "miu7r",
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.sid = TEGRA194_SID_MIU,
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.regs = {
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.sid = {
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.override = 0x008,
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.security = 0x00c,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_MIU7W,
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.name = "miu7w",
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.sid = TEGRA194_SID_MIU,
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.regs = {
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.sid = {
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.override = 0x010,
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.security = 0x014,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_HDAR,
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.name = "hdar",
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.sid = TEGRA194_SID_HDA,
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.regs = {
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.sid = {
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.override = 0x0a8,
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.security = 0x0ac,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_HOST1XDMAR,
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.name = "host1xdmar",
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.sid = TEGRA194_SID_HOST1X,
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.regs = {
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.sid = {
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.override = 0x0b0,
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.security = 0x0b4,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_NVENCSRD,
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.name = "nvencsrd",
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.sid = TEGRA194_SID_NVENC,
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.regs = {
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.sid = {
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.override = 0x0e0,
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.security = 0x0e4,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_SATAR,
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.name = "satar",
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.sid = TEGRA194_SID_SATA,
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.regs = {
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.sid = {
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.override = 0x0f8,
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.security = 0x0fc,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_MPCORER,
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.name = "mpcorer",
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.sid = TEGRA194_SID_PASSTHROUGH,
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.regs = {
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.sid = {
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.override = 0x138,
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.security = 0x13c,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_NVENCSWR,
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.name = "nvencswr",
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.sid = TEGRA194_SID_NVENC,
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.regs = {
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.sid = {
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.override = 0x158,
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.security = 0x15c,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_HDAW,
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.name = "hdaw",
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.sid = TEGRA194_SID_HDA,
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.regs = {
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.sid = {
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.override = 0x1a8,
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.security = 0x1ac,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_MPCOREW,
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.name = "mpcorew",
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.sid = TEGRA194_SID_PASSTHROUGH,
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.regs = {
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.sid = {
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.override = 0x1c8,
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.security = 0x1cc,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_SATAW,
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.name = "sataw",
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.sid = TEGRA194_SID_SATA,
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.regs = {
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.sid = {
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.override = 0x1e8,
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.security = 0x1ec,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_ISPRA,
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.name = "ispra",
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.sid = TEGRA194_SID_ISP,
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.regs = {
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.sid = {
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.override = 0x220,
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.security = 0x224,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_ISPFALR,
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.name = "ispfalr",
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.sid = TEGRA194_SID_ISP_FALCON,
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.regs = {
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.sid = {
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.override = 0x228,
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.security = 0x22c,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_ISPWA,
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.name = "ispwa",
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.sid = TEGRA194_SID_ISP,
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.regs = {
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.sid = {
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.override = 0x230,
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.security = 0x234,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_ISPWB,
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.name = "ispwb",
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.sid = TEGRA194_SID_ISP,
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.regs = {
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.sid = {
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.override = 0x238,
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.security = 0x23c,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTR,
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.name = "xusb_hostr",
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.sid = TEGRA194_SID_XUSB_HOST,
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.regs = {
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.sid = {
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.override = 0x250,
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.security = 0x254,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTW,
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.name = "xusb_hostw",
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.sid = TEGRA194_SID_XUSB_HOST,
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.regs = {
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.sid = {
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.override = 0x258,
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.security = 0x25c,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_XUSB_DEVR,
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.name = "xusb_devr",
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.sid = TEGRA194_SID_XUSB_DEV,
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.regs = {
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.sid = {
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.override = 0x260,
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.security = 0x264,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_XUSB_DEVW,
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.name = "xusb_devw",
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.sid = TEGRA194_SID_XUSB_DEV,
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.regs = {
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.sid = {
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.override = 0x268,
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.security = 0x26c,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_SDMMCRA,
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.name = "sdmmcra",
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.sid = TEGRA194_SID_SDMMC1,
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.regs = {
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.sid = {
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.override = 0x300,
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.security = 0x304,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_SDMMCR,
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.name = "sdmmcr",
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.sid = TEGRA194_SID_SDMMC3,
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.regs = {
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.sid = {
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.override = 0x310,
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.security = 0x314,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_SDMMCRAB,
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.name = "sdmmcrab",
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.sid = TEGRA194_SID_SDMMC4,
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.regs = {
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.sid = {
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.override = 0x318,
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.security = 0x31c,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_SDMMCWA,
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.name = "sdmmcwa",
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.sid = TEGRA194_SID_SDMMC1,
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.regs = {
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.sid = {
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.override = 0x320,
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.security = 0x324,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_SDMMCW,
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.name = "sdmmcw",
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.sid = TEGRA194_SID_SDMMC3,
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.regs = {
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.sid = {
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.override = 0x330,
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.security = 0x334,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_SDMMCWAB,
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.name = "sdmmcwab",
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.sid = TEGRA194_SID_SDMMC4,
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.regs = {
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.sid = {
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.override = 0x338,
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.security = 0x33c,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_VICSRD,
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.name = "vicsrd",
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.sid = TEGRA194_SID_VIC,
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.regs = {
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.sid = {
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.override = 0x360,
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.security = 0x364,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_VICSWR,
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.name = "vicswr",
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.sid = TEGRA194_SID_VIC,
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.regs = {
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.sid = {
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.override = 0x368,
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.security = 0x36c,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_VIW,
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.name = "viw",
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.sid = TEGRA194_SID_VI,
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.regs = {
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.sid = {
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.override = 0x390,
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.security = 0x394,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_NVDECSRD,
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.name = "nvdecsrd",
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.sid = TEGRA194_SID_NVDEC,
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.regs = {
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.sid = {
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.override = 0x3c0,
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.security = 0x3c4,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_NVDECSWR,
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.name = "nvdecswr",
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.sid = TEGRA194_SID_NVDEC,
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.regs = {
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.sid = {
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.override = 0x3c8,
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.security = 0x3cc,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_APER,
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.name = "aper",
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.sid = TEGRA194_SID_APE,
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.regs = {
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.sid = {
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.override = 0x3c0,
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.security = 0x3c4,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_APEW,
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.name = "apew",
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.sid = TEGRA194_SID_APE,
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.regs = {
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.sid = {
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.override = 0x3d0,
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.security = 0x3d4,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_NVJPGSRD,
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.name = "nvjpgsrd",
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.sid = TEGRA194_SID_NVJPG,
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.regs = {
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.sid = {
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.override = 0x3f0,
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.security = 0x3f4,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_NVJPGSWR,
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.name = "nvjpgswr",
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.sid = TEGRA194_SID_NVJPG,
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.regs = {
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.sid = {
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.override = 0x3f0,
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.security = 0x3f4,
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},
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},
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}, {
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.name = "axiapr",
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.id = TEGRA194_MEMORY_CLIENT_AXIAPR,
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.sid = TEGRA194_SID_PASSTHROUGH,
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.regs = {
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.sid = {
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.override = 0x410,
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.security = 0x414,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_AXIAPW,
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.name = "axiapw",
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.sid = TEGRA194_SID_PASSTHROUGH,
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.regs = {
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.sid = {
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.override = 0x418,
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.security = 0x41c,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_ETRR,
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.name = "etrr",
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.sid = TEGRA194_SID_ETR,
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.regs = {
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.sid = {
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.override = 0x420,
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.security = 0x424,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_ETRW,
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.name = "etrw",
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.sid = TEGRA194_SID_ETR,
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.regs = {
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.sid = {
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.override = 0x428,
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.security = 0x42c,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_AXISR,
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.name = "axisr",
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.sid = TEGRA194_SID_PASSTHROUGH,
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.regs = {
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.sid = {
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.override = 0x460,
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.security = 0x464,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_AXISW,
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.name = "axisw",
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.sid = TEGRA194_SID_PASSTHROUGH,
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.regs = {
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.sid = {
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.override = 0x468,
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.security = 0x46c,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_EQOSR,
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.name = "eqosr",
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.sid = TEGRA194_SID_EQOS,
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.regs = {
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.sid = {
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.override = 0x470,
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.security = 0x474,
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},
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},
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}, {
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.name = "eqosw",
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.id = TEGRA194_MEMORY_CLIENT_EQOSW,
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.sid = TEGRA194_SID_EQOS,
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.regs = {
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.sid = {
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.override = 0x478,
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.security = 0x47c,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_UFSHCR,
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.name = "ufshcr",
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.sid = TEGRA194_SID_UFSHC,
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.regs = {
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.sid = {
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.override = 0x480,
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.security = 0x484,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_UFSHCW,
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.name = "ufshcw",
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.sid = TEGRA194_SID_UFSHC,
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.regs = {
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.sid = {
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.override = 0x488,
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.security = 0x48c,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR,
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.name = "nvdisplayr",
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.sid = TEGRA194_SID_NVDISPLAY,
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.regs = {
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.sid = {
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.override = 0x490,
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.security = 0x494,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_BPMPR,
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.name = "bpmpr",
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.sid = TEGRA194_SID_BPMP,
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.regs = {
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.sid = {
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.override = 0x498,
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.security = 0x49c,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_BPMPW,
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.name = "bpmpw",
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.sid = TEGRA194_SID_BPMP,
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.regs = {
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.sid = {
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.override = 0x4a0,
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.security = 0x4a4,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_BPMPDMAR,
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.name = "bpmpdmar",
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.sid = TEGRA194_SID_BPMP,
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.regs = {
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.sid = {
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.override = 0x4a8,
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.security = 0x4ac,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_BPMPDMAW,
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.name = "bpmpdmaw",
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.sid = TEGRA194_SID_BPMP,
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.regs = {
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.sid = {
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.override = 0x4b0,
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.security = 0x4b4,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_AONR,
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.name = "aonr",
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.sid = TEGRA194_SID_AON,
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.regs = {
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.sid = {
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.override = 0x4b8,
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.security = 0x4bc,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_AONW,
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.name = "aonw",
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.sid = TEGRA194_SID_AON,
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.regs = {
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.sid = {
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.override = 0x4c0,
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.security = 0x4c4,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_AONDMAR,
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.name = "aondmar",
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.sid = TEGRA194_SID_AON,
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.regs = {
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.sid = {
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.override = 0x4c8,
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.security = 0x4cc,
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},
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},
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}, {
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.id = TEGRA194_MEMORY_CLIENT_AONDMAW,
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.name = "aondmaw",
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.sid = TEGRA194_SID_AON,
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.regs = {
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.sid = {
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.override = 0x4d0,
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.security = 0x4d4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_SCER,
|
|
.name = "scer",
|
|
.sid = TEGRA194_SID_SCE,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x4d8,
|
|
.security = 0x4dc,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_SCEW,
|
|
.name = "scew",
|
|
.sid = TEGRA194_SID_SCE,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x4e0,
|
|
.security = 0x4e4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_SCEDMAR,
|
|
.name = "scedmar",
|
|
.sid = TEGRA194_SID_SCE,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x4e8,
|
|
.security = 0x4ec,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_SCEDMAW,
|
|
.name = "scedmaw",
|
|
.sid = TEGRA194_SID_SCE,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x4f0,
|
|
.security = 0x4f4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_APEDMAR,
|
|
.name = "apedmar",
|
|
.sid = TEGRA194_SID_APE,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x4f8,
|
|
.security = 0x4fc,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_APEDMAW,
|
|
.name = "apedmaw",
|
|
.sid = TEGRA194_SID_APE,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x500,
|
|
.security = 0x504,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR1,
|
|
.name = "nvdisplayr1",
|
|
.sid = TEGRA194_SID_NVDISPLAY,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x508,
|
|
.security = 0x50c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_VICSRD1,
|
|
.name = "vicsrd1",
|
|
.sid = TEGRA194_SID_VIC,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x510,
|
|
.security = 0x514,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_NVDECSRD1,
|
|
.name = "nvdecsrd1",
|
|
.sid = TEGRA194_SID_NVDEC,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x518,
|
|
.security = 0x51c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_MIU0R,
|
|
.name = "miu0r",
|
|
.sid = TEGRA194_SID_MIU,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x530,
|
|
.security = 0x534,
|
|
},
|
|
},
|
|
}, {
|
|
.name = "miu0w",
|
|
.id = TEGRA194_MEMORY_CLIENT_MIU0W,
|
|
.sid = TEGRA194_SID_MIU,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x538,
|
|
.security = 0x53c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_MIU1R,
|
|
.name = "miu1r",
|
|
.sid = TEGRA194_SID_MIU,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x540,
|
|
.security = 0x544,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_MIU1W,
|
|
.name = "miu1w",
|
|
.sid = TEGRA194_SID_MIU,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x548,
|
|
.security = 0x54c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_MIU2R,
|
|
.name = "miu2r",
|
|
.sid = TEGRA194_SID_MIU,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x570,
|
|
.security = 0x574,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_MIU2W,
|
|
.name = "miu2w",
|
|
.sid = TEGRA194_SID_MIU,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x578,
|
|
.security = 0x57c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_MIU3R,
|
|
.name = "miu3r",
|
|
.sid = TEGRA194_SID_MIU,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x580,
|
|
.security = 0x584,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_MIU3W,
|
|
.name = "miu3w",
|
|
.sid = TEGRA194_SID_MIU,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x588,
|
|
.security = 0x58c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_MIU4R,
|
|
.name = "miu4r",
|
|
.sid = TEGRA194_SID_MIU,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x590,
|
|
.security = 0x594,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_MIU4W,
|
|
.name = "miu4w",
|
|
.sid = TEGRA194_SID_MIU,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x598,
|
|
.security = 0x59c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_DPMUR,
|
|
.name = "dpmur",
|
|
.sid = TEGRA194_SID_PASSTHROUGH,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x598,
|
|
.security = 0x59c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_VIFALR,
|
|
.name = "vifalr",
|
|
.sid = TEGRA194_SID_VI_FALCON,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x5e0,
|
|
.security = 0x5e4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_VIFALW,
|
|
.name = "vifalw",
|
|
.sid = TEGRA194_SID_VI_FALCON,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x5e8,
|
|
.security = 0x5ec,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_DLA0RDA,
|
|
.name = "dla0rda",
|
|
.sid = TEGRA194_SID_NVDLA0,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x5f0,
|
|
.security = 0x5f4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_DLA0FALRDB,
|
|
.name = "dla0falrdb",
|
|
.sid = TEGRA194_SID_NVDLA0,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x5f8,
|
|
.security = 0x5fc,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_DLA0WRA,
|
|
.name = "dla0wra",
|
|
.sid = TEGRA194_SID_NVDLA0,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x600,
|
|
.security = 0x604,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_DLA0FALWRB,
|
|
.name = "dla0falwrb",
|
|
.sid = TEGRA194_SID_NVDLA0,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x608,
|
|
.security = 0x60c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_DLA1RDA,
|
|
.name = "dla1rda",
|
|
.sid = TEGRA194_SID_NVDLA1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x610,
|
|
.security = 0x614,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_DLA1FALRDB,
|
|
.name = "dla1falrdb",
|
|
.sid = TEGRA194_SID_NVDLA1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x618,
|
|
.security = 0x61c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_DLA1WRA,
|
|
.name = "dla1wra",
|
|
.sid = TEGRA194_SID_NVDLA1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x620,
|
|
.security = 0x624,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_DLA1FALWRB,
|
|
.name = "dla1falwrb",
|
|
.sid = TEGRA194_SID_NVDLA1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x628,
|
|
.security = 0x62c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PVA0RDA,
|
|
.name = "pva0rda",
|
|
.sid = TEGRA194_SID_PVA0,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x630,
|
|
.security = 0x634,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PVA0RDB,
|
|
.name = "pva0rdb",
|
|
.sid = TEGRA194_SID_PVA0,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x638,
|
|
.security = 0x63c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PVA0RDC,
|
|
.name = "pva0rdc",
|
|
.sid = TEGRA194_SID_PVA0,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x640,
|
|
.security = 0x644,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PVA0WRA,
|
|
.name = "pva0wra",
|
|
.sid = TEGRA194_SID_PVA0,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x648,
|
|
.security = 0x64c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PVA0WRB,
|
|
.name = "pva0wrb",
|
|
.sid = TEGRA194_SID_PVA0,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x650,
|
|
.security = 0x654,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PVA0WRC,
|
|
.name = "pva0wrc",
|
|
.sid = TEGRA194_SID_PVA0,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x658,
|
|
.security = 0x65c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PVA1RDA,
|
|
.name = "pva1rda",
|
|
.sid = TEGRA194_SID_PVA1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x660,
|
|
.security = 0x664,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PVA1RDB,
|
|
.name = "pva1rdb",
|
|
.sid = TEGRA194_SID_PVA1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x668,
|
|
.security = 0x66c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PVA1RDC,
|
|
.name = "pva1rdc",
|
|
.sid = TEGRA194_SID_PVA1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x670,
|
|
.security = 0x674,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PVA1WRA,
|
|
.name = "pva1wra",
|
|
.sid = TEGRA194_SID_PVA1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x678,
|
|
.security = 0x67c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PVA1WRB,
|
|
.name = "pva1wrb",
|
|
.sid = TEGRA194_SID_PVA1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x680,
|
|
.security = 0x684,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PVA1WRC,
|
|
.name = "pva1wrc",
|
|
.sid = TEGRA194_SID_PVA1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x688,
|
|
.security = 0x68c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_RCER,
|
|
.name = "rcer",
|
|
.sid = TEGRA194_SID_RCE,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x690,
|
|
.security = 0x694,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_RCEW,
|
|
.name = "rcew",
|
|
.sid = TEGRA194_SID_RCE,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x698,
|
|
.security = 0x69c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_RCEDMAR,
|
|
.name = "rcedmar",
|
|
.sid = TEGRA194_SID_RCE,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6a0,
|
|
.security = 0x6a4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_RCEDMAW,
|
|
.name = "rcedmaw",
|
|
.sid = TEGRA194_SID_RCE,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6a8,
|
|
.security = 0x6ac,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_NVENC1SRD,
|
|
.name = "nvenc1srd",
|
|
.sid = TEGRA194_SID_NVENC1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6b0,
|
|
.security = 0x6b4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_NVENC1SWR,
|
|
.name = "nvenc1swr",
|
|
.sid = TEGRA194_SID_NVENC1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6b8,
|
|
.security = 0x6bc,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PCIE0R,
|
|
.name = "pcie0r",
|
|
.sid = TEGRA194_SID_PCIE0,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6c0,
|
|
.security = 0x6c4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PCIE0W,
|
|
.name = "pcie0w",
|
|
.sid = TEGRA194_SID_PCIE0,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6c8,
|
|
.security = 0x6cc,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PCIE1R,
|
|
.name = "pcie1r",
|
|
.sid = TEGRA194_SID_PCIE1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6d0,
|
|
.security = 0x6d4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PCIE1W,
|
|
.name = "pcie1w",
|
|
.sid = TEGRA194_SID_PCIE1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6d8,
|
|
.security = 0x6dc,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PCIE2AR,
|
|
.name = "pcie2ar",
|
|
.sid = TEGRA194_SID_PCIE2,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6e0,
|
|
.security = 0x6e4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PCIE2AW,
|
|
.name = "pcie2aw",
|
|
.sid = TEGRA194_SID_PCIE2,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6e8,
|
|
.security = 0x6ec,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PCIE3R,
|
|
.name = "pcie3r",
|
|
.sid = TEGRA194_SID_PCIE3,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6f0,
|
|
.security = 0x6f4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PCIE3W,
|
|
.name = "pcie3w",
|
|
.sid = TEGRA194_SID_PCIE3,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x6f8,
|
|
.security = 0x6fc,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PCIE4R,
|
|
.name = "pcie4r",
|
|
.sid = TEGRA194_SID_PCIE4,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x700,
|
|
.security = 0x704,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PCIE4W,
|
|
.name = "pcie4w",
|
|
.sid = TEGRA194_SID_PCIE4,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x708,
|
|
.security = 0x70c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PCIE5R,
|
|
.name = "pcie5r",
|
|
.sid = TEGRA194_SID_PCIE5,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x710,
|
|
.security = 0x714,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PCIE5W,
|
|
.name = "pcie5w",
|
|
.sid = TEGRA194_SID_PCIE5,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x718,
|
|
.security = 0x71c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_ISPFALW,
|
|
.name = "ispfalw",
|
|
.sid = TEGRA194_SID_ISP_FALCON,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x720,
|
|
.security = 0x724,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_DLA0RDA1,
|
|
.name = "dla0rda1",
|
|
.sid = TEGRA194_SID_NVDLA0,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x748,
|
|
.security = 0x74c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_DLA1RDA1,
|
|
.name = "dla1rda1",
|
|
.sid = TEGRA194_SID_NVDLA1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x750,
|
|
.security = 0x754,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PVA0RDA1,
|
|
.name = "pva0rda1",
|
|
.sid = TEGRA194_SID_PVA0,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x758,
|
|
.security = 0x75c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PVA0RDB1,
|
|
.name = "pva0rdb1",
|
|
.sid = TEGRA194_SID_PVA0,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x760,
|
|
.security = 0x764,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PVA1RDA1,
|
|
.name = "pva1rda1",
|
|
.sid = TEGRA194_SID_PVA1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x768,
|
|
.security = 0x76c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PVA1RDB1,
|
|
.name = "pva1rdb1",
|
|
.sid = TEGRA194_SID_PVA1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x770,
|
|
.security = 0x774,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PCIE5R1,
|
|
.name = "pcie5r1",
|
|
.sid = TEGRA194_SID_PCIE5,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x778,
|
|
.security = 0x77c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_NVENCSRD1,
|
|
.name = "nvencsrd1",
|
|
.sid = TEGRA194_SID_NVENC,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x780,
|
|
.security = 0x784,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_NVENC1SRD1,
|
|
.name = "nvenc1srd1",
|
|
.sid = TEGRA194_SID_NVENC1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x788,
|
|
.security = 0x78c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_ISPRA1,
|
|
.name = "ispra1",
|
|
.sid = TEGRA194_SID_ISP,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x790,
|
|
.security = 0x794,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_PCIE0R1,
|
|
.name = "pcie0r1",
|
|
.sid = TEGRA194_SID_PCIE0,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x798,
|
|
.security = 0x79c,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD,
|
|
.name = "nvdec1srd",
|
|
.sid = TEGRA194_SID_NVDEC1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x7c8,
|
|
.security = 0x7cc,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD1,
|
|
.name = "nvdec1srd1",
|
|
.sid = TEGRA194_SID_NVDEC1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x7d0,
|
|
.security = 0x7d4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_NVDEC1SWR,
|
|
.name = "nvdec1swr",
|
|
.sid = TEGRA194_SID_NVDEC1,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x7d8,
|
|
.security = 0x7dc,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_MIU5R,
|
|
.name = "miu5r",
|
|
.sid = TEGRA194_SID_MIU,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x7e0,
|
|
.security = 0x7e4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_MIU5W,
|
|
.name = "miu5w",
|
|
.sid = TEGRA194_SID_MIU,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x7e8,
|
|
.security = 0x7ec,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_MIU6R,
|
|
.name = "miu6r",
|
|
.sid = TEGRA194_SID_MIU,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x7f0,
|
|
.security = 0x7f4,
|
|
},
|
|
},
|
|
}, {
|
|
.id = TEGRA194_MEMORY_CLIENT_MIU6W,
|
|
.name = "miu6w",
|
|
.sid = TEGRA194_SID_MIU,
|
|
.regs = {
|
|
.sid = {
|
|
.override = 0x7f8,
|
|
.security = 0x7fc,
|
|
},
|
|
},
|
|
},
|
|
};
|
|
|
|
const struct tegra_mc_soc tegra194_mc_soc = {
|
|
.num_clients = ARRAY_SIZE(tegra194_mc_clients),
|
|
.clients = tegra194_mc_clients,
|
|
.num_address_bits = 40,
|
|
.num_channels = 16,
|
|
.client_id_mask = 0xff,
|
|
.intmask = MC_INT_DECERR_ROUTE_SANITY |
|
|
MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
|
|
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
|
|
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
|
|
.has_addr_hi_reg = true,
|
|
.ops = &tegra186_mc_ops,
|
|
.icc_ops = &tegra_mc_icc_ops,
|
|
.ch_intmask = 0x00000f00,
|
|
.global_intstatus_channel_shift = 8,
|
|
};
|