189 lines
		
	
	
		
			4.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			189 lines
		
	
	
		
			4.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0
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| /*
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|  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
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|  * Copyright (c) 2015, Sony Mobile Communications AB
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|  */
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| 
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| #include <linux/hwspinlock.h>
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| #include <linux/io.h>
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| #include <linux/kernel.h>
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| #include <linux/mfd/syscon.h>
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| #include <linux/module.h>
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| #include <linux/of.h>
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| #include <linux/of_device.h>
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| #include <linux/platform_device.h>
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| #include <linux/regmap.h>
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| 
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| #include "hwspinlock_internal.h"
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| 
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| #define QCOM_MUTEX_APPS_PROC_ID	1
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| #define QCOM_MUTEX_NUM_LOCKS	32
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| 
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| static int qcom_hwspinlock_trylock(struct hwspinlock *lock)
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| {
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| 	struct regmap_field *field = lock->priv;
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| 	u32 lock_owner;
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| 	int ret;
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| 
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| 	ret = regmap_field_write(field, QCOM_MUTEX_APPS_PROC_ID);
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| 	if (ret)
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| 		return ret;
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| 
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| 	ret = regmap_field_read(field, &lock_owner);
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| 	if (ret)
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| 		return ret;
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| 
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| 	return lock_owner == QCOM_MUTEX_APPS_PROC_ID;
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| }
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| 
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| static void qcom_hwspinlock_unlock(struct hwspinlock *lock)
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| {
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| 	struct regmap_field *field = lock->priv;
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| 	u32 lock_owner;
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| 	int ret;
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| 
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| 	ret = regmap_field_read(field, &lock_owner);
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| 	if (ret) {
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| 		pr_err("%s: unable to query spinlock owner\n", __func__);
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| 		return;
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| 	}
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| 
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| 	if (lock_owner != QCOM_MUTEX_APPS_PROC_ID) {
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| 		pr_err("%s: spinlock not owned by us (actual owner is %d)\n",
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| 				__func__, lock_owner);
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| 	}
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| 
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| 	ret = regmap_field_write(field, 0);
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| 	if (ret)
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| 		pr_err("%s: failed to unlock spinlock\n", __func__);
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| }
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| 
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| static const struct hwspinlock_ops qcom_hwspinlock_ops = {
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| 	.trylock	= qcom_hwspinlock_trylock,
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| 	.unlock		= qcom_hwspinlock_unlock,
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| };
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| 
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| static const struct of_device_id qcom_hwspinlock_of_match[] = {
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| 	{ .compatible = "qcom,sfpb-mutex" },
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| 	{ .compatible = "qcom,tcsr-mutex" },
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| 	{ }
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| };
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| MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match);
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| 
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| static struct regmap *qcom_hwspinlock_probe_syscon(struct platform_device *pdev,
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| 						   u32 *base, u32 *stride)
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| {
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| 	struct device_node *syscon;
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| 	struct regmap *regmap;
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| 	int ret;
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| 
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| 	syscon = of_parse_phandle(pdev->dev.of_node, "syscon", 0);
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| 	if (!syscon)
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| 		return ERR_PTR(-ENODEV);
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| 
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| 	regmap = syscon_node_to_regmap(syscon);
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| 	of_node_put(syscon);
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| 	if (IS_ERR(regmap))
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| 		return regmap;
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| 
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| 	ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, base);
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| 	if (ret < 0) {
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| 		dev_err(&pdev->dev, "no offset in syscon\n");
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| 		return ERR_PTR(-EINVAL);
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| 	}
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| 
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| 	ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, stride);
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| 	if (ret < 0) {
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| 		dev_err(&pdev->dev, "no stride syscon\n");
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| 		return ERR_PTR(-EINVAL);
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| 	}
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| 
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| 	return regmap;
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| }
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| 
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| static const struct regmap_config tcsr_mutex_config = {
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| 	.reg_bits		= 32,
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| 	.reg_stride		= 4,
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| 	.val_bits		= 32,
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| 	.max_register		= 0x40000,
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| 	.fast_io		= true,
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| };
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| 
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| static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev,
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| 						 u32 *offset, u32 *stride)
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| {
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| 	struct device *dev = &pdev->dev;
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| 	void __iomem *base;
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| 
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| 	/* All modern platform has offset 0 and stride of 4k */
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| 	*offset = 0;
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| 	*stride = 0x1000;
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| 
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| 	base = devm_platform_ioremap_resource(pdev, 0);
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| 	if (IS_ERR(base))
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| 		return ERR_CAST(base);
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| 
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| 	return devm_regmap_init_mmio(dev, base, &tcsr_mutex_config);
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| }
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| 
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| static int qcom_hwspinlock_probe(struct platform_device *pdev)
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| {
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| 	struct hwspinlock_device *bank;
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| 	struct reg_field field;
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| 	struct regmap *regmap;
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| 	size_t array_size;
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| 	u32 stride;
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| 	u32 base;
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| 	int i;
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| 
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| 	regmap = qcom_hwspinlock_probe_syscon(pdev, &base, &stride);
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| 	if (IS_ERR(regmap) && PTR_ERR(regmap) == -ENODEV)
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| 		regmap = qcom_hwspinlock_probe_mmio(pdev, &base, &stride);
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| 
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| 	if (IS_ERR(regmap))
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| 		return PTR_ERR(regmap);
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| 
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| 	array_size = QCOM_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock);
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| 	bank = devm_kzalloc(&pdev->dev, sizeof(*bank) + array_size, GFP_KERNEL);
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| 	if (!bank)
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| 		return -ENOMEM;
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| 
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| 	platform_set_drvdata(pdev, bank);
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| 
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| 	for (i = 0; i < QCOM_MUTEX_NUM_LOCKS; i++) {
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| 		field.reg = base + i * stride;
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| 		field.lsb = 0;
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| 		field.msb = 31;
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| 
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| 		bank->lock[i].priv = devm_regmap_field_alloc(&pdev->dev,
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| 							     regmap, field);
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| 	}
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| 
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| 	return devm_hwspin_lock_register(&pdev->dev, bank, &qcom_hwspinlock_ops,
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| 					 0, QCOM_MUTEX_NUM_LOCKS);
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| }
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| 
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| static struct platform_driver qcom_hwspinlock_driver = {
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| 	.probe		= qcom_hwspinlock_probe,
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| 	.driver		= {
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| 		.name	= "qcom_hwspinlock",
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| 		.of_match_table = qcom_hwspinlock_of_match,
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| 	},
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| };
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| 
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| static int __init qcom_hwspinlock_init(void)
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| {
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| 	return platform_driver_register(&qcom_hwspinlock_driver);
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| }
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| /* board init code might need to reserve hwspinlocks for predefined purposes */
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| postcore_initcall(qcom_hwspinlock_init);
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| 
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| static void __exit qcom_hwspinlock_exit(void)
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| {
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| 	platform_driver_unregister(&qcom_hwspinlock_driver);
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| }
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| module_exit(qcom_hwspinlock_exit);
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| 
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| MODULE_LICENSE("GPL v2");
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| MODULE_DESCRIPTION("Hardware spinlock driver for Qualcomm SoCs");
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