89 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			89 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0-or-later
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| /*
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|  * Copyright (C) 2016 Socionext Inc.
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|  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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|  */
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| 
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| #include <linux/clk-provider.h>
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| #include <linux/device.h>
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| #include <linux/regmap.h>
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| 
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| #include "clk-uniphier.h"
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| 
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| struct uniphier_clk_gate {
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| 	struct clk_hw hw;
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| 	struct regmap *regmap;
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| 	unsigned int reg;
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| 	unsigned int bit;
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| };
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| 
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| #define to_uniphier_clk_gate(_hw) \
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| 				container_of(_hw, struct uniphier_clk_gate, hw)
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| 
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| static int uniphier_clk_gate_endisable(struct clk_hw *hw, int enable)
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| {
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| 	struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
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| 
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| 	return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit),
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| 				 enable ? BIT(gate->bit) : 0);
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| }
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| 
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| static int uniphier_clk_gate_enable(struct clk_hw *hw)
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| {
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| 	return uniphier_clk_gate_endisable(hw, 1);
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| }
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| 
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| static void uniphier_clk_gate_disable(struct clk_hw *hw)
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| {
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| 	if (uniphier_clk_gate_endisable(hw, 0) < 0)
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| 		pr_warn("failed to disable clk\n");
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| }
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| 
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| static int uniphier_clk_gate_is_enabled(struct clk_hw *hw)
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| {
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| 	struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
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| 	unsigned int val;
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| 
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| 	if (regmap_read(gate->regmap, gate->reg, &val) < 0)
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| 		pr_warn("is_enabled() may return wrong result\n");
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| 
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| 	return !!(val & BIT(gate->bit));
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| }
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| 
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| static const struct clk_ops uniphier_clk_gate_ops = {
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| 	.enable = uniphier_clk_gate_enable,
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| 	.disable = uniphier_clk_gate_disable,
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| 	.is_enabled = uniphier_clk_gate_is_enabled,
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| };
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| 
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| struct clk_hw *uniphier_clk_register_gate(struct device *dev,
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| 					  struct regmap *regmap,
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| 					  const char *name,
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| 				const struct uniphier_clk_gate_data *data)
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| {
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| 	struct uniphier_clk_gate *gate;
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| 	struct clk_init_data init;
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| 	int ret;
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| 
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| 	gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
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| 	if (!gate)
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| 		return ERR_PTR(-ENOMEM);
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| 
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| 	init.name = name;
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| 	init.ops = &uniphier_clk_gate_ops;
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| 	init.flags = data->parent_name ? CLK_SET_RATE_PARENT : 0;
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| 	init.parent_names = data->parent_name ? &data->parent_name : NULL;
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| 	init.num_parents = data->parent_name ? 1 : 0;
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| 
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| 	gate->regmap = regmap;
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| 	gate->reg = data->reg;
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| 	gate->bit = data->bit;
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| 	gate->hw.init = &init;
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| 
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| 	ret = devm_clk_hw_register(dev, &gate->hw);
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| 	if (ret)
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| 		return ERR_PTR(ret);
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| 
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| 	return &gate->hw;
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| }
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